Datasheet > MN101EF94F

MN101EF94F

更新时间： 2024-11-16 01:13:59

品牌	Logo	应用领域
松下 - PANASONIC		微控制器
页数	文件大小	规格书
32页	353K
描述
8-bit Single-chip Microcontroller

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MN101EF94F 数据手册

MN101EF94 Series

8-bit Single-chip Microcontroller

PubNo. 21694-012E

1.1 Overview

1.1.1

Overview

The MN101E series of 8-bit single-chip microcomputers (the memory expansion version of MN101C series)

incorporate multiple types of peripheral functions. This chip series is well suited for camera, VCR, MD, TV, CD,

LD, printer, telephone, home automation, pager, air conditioner, PPC, fax machine, music instrument and other

applications.

This LSI brings to embedded microcomputer applications flexible, optimized hardware configurations and a sim-

ple efficient instruction set. MN101EF94G has an internal 128 KB of ROM and 6 KB of RAM. MN101EF94F

has an internal 96 KB of ROM and 6 KB of RAM. Peripheral functions include 5 external interrupts, 29 internal

interrupts including NMI, 11 timer counters, 6 types of serial interfaces, A/D converter, LCD driver, 2 types of

watchdog timer, data automatic function and buzzer output. The system configuration is suitable for in camera,

timer selector for VCR, CD player, or minicomponent.

With 5 oscillation systems (high-speed (internal frequency: 20 MHz), high-speed (crystal/ceramic frequency:

max. 10 MHz) / low-speed (internal frequency: 30 kHz), low-speed (crystal/ceramic frequency: 32.768 kHz) and

PLL: frequency multiplier of high frequency) contained on the chip, the system clock can be switched to high-

speed frequency input (NORMAL mode), PLL input (PLL mode), or to low-speed frequency input (SLOW

mode). The system clock is generated by dividing the oscillation clock or PLL clock. The best operation clock for

the system can be selected by switching its frequency ratio by programming. High speed mode has the normal

mode which is based on the clock dividing fpll, (fpll is generated by original oscillation and PLL), by 2 (fpll/2),

and the double speed mode which is based on the clock not dividing fpll.

A machine cycle (minimum instruction execution time) in the normal mode is 200 ns when the original oscillation

fosc is 10 MHz (PLL is not used). A machine cycle in the double speed mode, in which the CPU operates on the

same clock as the external clock, is 100 ns when fosc is 10 MHz. A machine cycle in the PLL mode is 50 ns (max-

imum).

1.1.2

Product Summary

This manual describes the following model.

Table:1.1.1 Product Summary

Model

ROM Size RAM Size

Classification

Package

MN101EF94G

MN101EF94F

128 KB

96 KB

6 KB

Flash EEPROM version 100 Pin LQFP

Publication date: February 2015

12 3 4 5 6 7...32

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与MN101EF94F相关器件

型号	品牌	获取价格	描述	数据表
MN101EF94G	PANASONIC	获取价格	8-bit Single-chip Microcontroller
MN101EFA0A	PANASONIC	获取价格	8-bit Single-chip Microcontroller
MN101EFA1A	PANASONIC	获取价格	8-bit Single-chip Microcontroller
MN101EFA2D	PANASONIC	获取价格	8-bit Single-chip Microcontroller
MN101EFA2G	PANASONIC	获取价格	8-bit Single-chip Microcontroller
MN101EFA3D	PANASONIC	获取价格	8-bit Single-chip Microcontroller
MN101EFA3G	PANASONIC	获取价格	8-bit Single-chip Microcontroller
MN101EFA5A	PANASONIC	获取价格	8-bit Single-chip Microcontroller
MN101EFA6	PANASONIC	获取价格	8-bit Single-chip Microcontroller
MN101EFA6A	PANASONIC	获取价格	8-bit Single-chip Microcontroller

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