Datasheet > MN101EF76K

MN101EF76K

更新时间： 2024-11-16 01:07:43

品牌	Logo	应用领域
松下 - PANASONIC		微控制器
页数	文件大小	规格书
13页	473K
描述
8-bit Single-chip Microcontroller

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MN101EF76K 数据手册

MN101E56/57/76 Series

8-bit Single-chip Microcontroller

 Overview

The MN101E series of 8-bit single-chip microcomputers (the memory expansion version of MN101C series) incorporate multiple types

of peripheral functions. This chip series is well suited for camera, VCR, MD, TV, CD, LD, printer, telephone, home automation, pager, air

conditioner, PPC, fax machine, music instrument and other applications.

This LSI brings to embedded microcomputer applications flexible, optimized hardware configurations and a simple efficient instruction

set. MN101EF57 series has an internal 128 KB of ROM and 6 KB of RAM. Peripheral functions include 5 external interrupts, 29 internal

interrupts including NMI, 12 timer counters, 4 types of serial interfaces, A/D converter, D/A converter, LCD driver, 2 types of watchdog

timer, data automatic function and buzzer output. The system conﬁguration is suitable for in camera, timer selector for VCR, CD player, or

minicomponent.

With 5 oscillation systems (high-speed (internal frequency: 20 MHz), high-speed (crystal/ceramic frequency: max. 10 MHz) / low-speed

(internal frequency: 30 kHz), low-speed (crystal/ceramic frequency: 32.768 kHz) and PLL: frequency multiplier of high frequency) contained

on the chip, the system clock can be switched to high-speed frequency input (NORMAL mode), PLL input (PLL mode), or to low-speed

frequency input (SLOW mode). The system clock is generated by dividing the oscillation clock or PLL clock. The best operation clock for the

system can be selected by switching its frequency ratio by programming. High speed mode has the normal mode which is based on the clock

dividing fpll, (fpll is generated by original oscillation and PLL), by 2 (fpll/2), and the double speed mode which is based on the clock not

dividing fpll.

A machine cycle (minimum instruction execution time) in the normal mode is 200 ns when the original oscillation fosc is 10 MHz (PLL is not

used). A machine cycle in the double speed mode, in which the CPU operates on the same clock as the external clock, is 100 ns when fosc is

10 MHz. A machine cycle in the PLL mode is 50 ns (maximum).

 Product Summary

This datasheet describes the following model.

Model

ROM Size

RAM Size

Classiﬁcation

Package

MN101EF76K

256 KB

10 KB

LQFP128-P-1818C

LQFP080-P-1414A

TQFP080-P-1212F

MN101EF57G

128 KB

6 KB

Flash EEPROM version

MN101EF56K

256 KB

10 KB

QFP100-P-1818B

Note) DMOD internal pull-up resistor is in only Flash EEPROM version.

When using In-circuit Emulator, it is necessary to connect the pull-up resistor on the circuit board.

Publication date: February 2014

Ver. BEM

12 3 4 5 6 7...13

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MN101EFA2G	PANASONIC	获取价格	8-bit Single-chip Microcontroller
MN101EFA3D	PANASONIC	获取价格	8-bit Single-chip Microcontroller

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