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MN101EF50D PDF预览

MN101EF50D

更新时间: 2024-11-16 01:15:47
品牌 Logo 应用领域
松下 - PANASONIC 时钟微控制器外围集成电路
页数 文件大小 规格书
9页 572K
描述
8-bit Single-chip Microcontroller

MN101EF50D 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFP
包装说明:LQFP-64针数:64
Reach Compliance Code:compliantHTS代码:8542.31.00.01
风险等级:5.79具有ADC:YES
其他特性:ALSO OPERATES AT 1.8 V MINIMUM SUPPLY AT 8 MHZ地址总线宽度:
位大小:8最大时钟频率:10 MHz
DAC 通道:NODMA 通道:NO
外部数据总线宽度:JESD-30 代码:S-PQFP-G64
长度:14 mmI/O 线路数量:55
端子数量:64最高工作温度:85 °C
最低工作温度:-40 °CPWM 通道:YES
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:QFP64,.63SQ,32封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/5 V认证状态:Not Qualified
RAM(字节):4096ROM(单词):65536
ROM可编程性:FLASH座面最大高度:1.7 mm
速度:20 MHz子类别:Microcontrollers
最大供电电压:5.5 V最小供电电压:2.7 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.8 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
uPs/uCs/外围集成电路类型:MICROCONTROLLERBase Number Matches:1

MN101EF50D 数据手册

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MN101E50 Series  
8-bit Single-chip Microcontroller  
Overview  
The MN101E series of 8-bit single-chip microcomputers (the memory expansion version of MN101C series) incorporate  
multiple types of peripheral functions. This chip series is well suited for camera, VCR, MD, TV, CD, LD, printer, telephone,  
home automation, pager, air conditioner, PPC, fax machine, music instrument and other electrical appliances.  
This LSI has embedded exible microcomputer applications, optimized hardware congurations and a simple yet efcient  
instruction set. MN101EF50D has an internal 64 KB of ROM and 4 KB of RAM. Peripheral functions include 5 external  
interrupts, 25 internal interrupts including NMI, 11 timer counters, 4 types of serial interfaces, A/D converter, LCD driver,  
watchdog timer and buzzer output. The system conguration is suitable for system control microcontrollers such as cameras,  
timer selectors for VCR, CD players or minicomponents.  
With 4 oscillation systems (high-speed internal frequency: 20 MHz, high-speed crystal/ceramic frequency: max. 10 MHz /  
low-speed crystal/ceramic frequency: 32.768 kHz and PLL: frequency multiplier of the high-speed frequency) contained in the  
chip, the system clock can be switched to high-speed frequency input (NORMAL mode), PLL input (PLL mode) or low-speed  
frequency input (SLOW mode). The system clock is generated by dividing the oscillation clock or PLL clock. The optimum  
operating clock for the system can be selected by switching its frequency ratio by programming.  
The machine cycle (minimum instruction execution time) is 100 ns when the external oscillation fosc is 10 MHz (PLL is not  
used). The machine cycle is 50 ns (maximum) when the internal oscillation frequency is 20 MHz (PLL is not used). A machine  
cycle in the PLL mode is 50 ns (maximum).  
Product Summary  
This datasheet describes the following model.  
Model  
ROM Size  
RAM Size  
Classication  
Package  
MN101EF50D  
64 KB  
4 KB  
Flash EEPROM version  
LQFP064-P-1414  
Publication date: November 2011  
Ver. AEM  
1

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