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MMQR-67025L-25 PDF预览

MMQR-67025L-25

更新时间： 2024-11-01 19:21:19
品牌 Logo 应用领域
TEMIC 静态存储器内存集成电路
页数 文件大小 规格书
23页 257K
描述
Dual-Port SRAM, 8KX16, 25ns, CMOS, CQCC84, CERAMIC, QUAD-84

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中文翻译

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MMQR-67025L-25 技术参数

是否Rohs认证：不符合生命周期：Transferred
包装说明：CERAMIC, QUAD-84Reach Compliance Code：unknown
风险等级：5.83Is Samacsys：N
最长访问时间：25 nsI/O 类型：COMMON
JESD-30 代码：S-GQCC-J84JESD-609代码：e0
内存密度：131072 bit内存集成电路类型：DUAL-PORT SRAM
内存宽度：16功能数量：1
端口数量：2端子数量：84
字数：8192 words字数代码：8000
工作模式：ASYNCHRONOUS最高工作温度：125 °C
最低工作温度：-55 °C组织：8KX16
输出特性：3-STATE封装主体材料：CERAMIC, GLASS-SEALED
封装代码：QCCJ封装等效代码：LDCC84,1.2SQ
封装形状：SQUARE封装形式：CHIP CARRIER
并行/串行：PARALLEL电源：5 V
认证状态：Not Qualified最大待机电流：0.0004 A
最小待机电流：2 V子类别：SRAMs
最大压摆率：0.37 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：J BEND端子节距：1.27 mm
端子位置：QUADBase Number Matches：1

MMQR-67025L-25 数据手册

 浏览型号MMQR-67025L-25的Datasheet PDF文件第2页浏览型号MMQR-67025L-25的Datasheet PDF文件第3页浏览型号MMQR-67025L-25的Datasheet PDF文件第4页浏览型号MMQR-67025L-25的Datasheet PDF文件第5页浏览型号MMQR-67025L-25的Datasheet PDF文件第6页浏览型号MMQR-67025L-25的Datasheet PDF文件第7页 
MATRA MHS  
M 67025  
8 K × 16 CMOS Dual Port RAM  
Introduction  
The M 67025 is a very low power CMOS dual port static Using an array of eigh transistors (8T) memory cell and  
RAM organised as 8192 × 16. The M 67025 is designed fabricated with the state of the art 0.65 µ lithography  
to be used as a stand-alone 16 bit dual port RAM or as a named SCMOS, the M 67025 combines an extremely low  
combination MASTER/SLAVE dual port for 32 bit or standby supply current (typ = 1.0 µA) with a fast access  
more  
width  
systems.  
The  
MATRA-MHS time at 20 ns over the full temperature range. All versions  
MASTER/SLAVE dual port approach in memory system offer battery backup data retention capability with a  
applications results in full speed, error free operation typical power consumption at less than 5 µW.  
without the need of an additional discrete logic.  
For military/space applications that demand superior  
Master and slave devices provide two independant ports  
with separate control, address and I/O pins that permit  
independant, asynchronous access for reads and writes to  
any location in the memory. An automatic power down  
feature controlled by CS permits the on-chip circuitry of  
each port in order to enter a very low stand by power  
mode.  
levels of performance and reliability the M 67025 is  
processed according to the methods of the latest revision  
of the MIL STD 883 (class B or S) and/or ESA SCC 9000.  
Features  
D Fast access time : 20/25/30/35/45/55 ns  
D Wide temperature range :  
D Versatile pin select for master or slave :  
– M/S = H for busy output flag on master  
– M/S = L for busy input flag on slave  
–55 °C to +125 °C  
D 67025 L low power  
D INT flag for port to port communication  
D Full hardware support of semaphore signaling between ports  
D Fully asynchronous operation from either port  
D Battery back-up operation : 2 V data retention  
D TTL compatible  
67025 V very low power  
D Separate upper byte and lower byte control for multiplexed  
bus compatibility  
D Expandable data bus to 32 bits or more using master/slave  
chip select when using more than one device  
D On chip arbitration logic  
D Single 5 V ± 10 % power supply  
D For 3.3 V version, please consult sales  
Rev. D (29/09/95)  
1
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