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MM54C195W/883 PDF预览

MM54C195W/883

更新时间: 2024-11-16 19:56:31
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER /
页数 文件大小 规格书
6页 17K
描述
Parallel In Parallel Out

MM54C195W/883 技术参数

生命周期:Contact Manufacturer包装说明:,
Reach Compliance Code:unknown风险等级:5.77
Base Number Matches:1

MM54C195W/883 数据手册

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MICROCIRCUIT DATA SHEET  
Original Creation Date: 10/18/95  
Last Update Date: 05/19/97  
MNMM54C195-X REV 1A0  
Last Major Revision Date: 04/02/97  
4-BIT REGISTERS  
General Description  
The MM54C195 CMOS 4-bit registers feature parallel inputs, parallel outputs, J-K serial  
inputs, shift/load control input and a direct overriding clear. The following two modes of  
operation are possible:  
Parallel Load  
Shift in direction QA towards QD  
Parallel loading is accomplished by applying the four bits of data and taking the  
shift/load control of input low. The data is loaded into the associated flip-flops and  
appears at the outputs after the positive transition of the clock input. During parallel  
loading, serial data flow is inhibited.  
Serial shifting is accomplished synchronously when the shift/load control input is high.  
Serial data for this mode is entered at the J-K inputs. These inputs allow the first stage  
to perform as a J-K, D, or T-type flip flop as shown in the truth table.  
Industry Part Number  
NS Part Numbers  
MM54C195  
MM54C195J/883  
MM54C195W/883  
Prime Die  
MM54C195  
Processing  
Subgrp Description  
Temp (oC)  
MIL-STD-883, Method 5004  
1
Static tests at  
+25  
2
Static tests at  
+125  
-55  
3
Static tests at  
4
Dynamic tests at  
Dynamic tests at  
Dynamic tests at  
Functional tests at  
Functional tests at  
Functional tests at  
Switching tests at  
Switching tests at  
Switching tests at  
+25  
Quality Conformance Inspection  
5
+125  
-55  
6
MIL-STD-883, Method 5005  
7
+25  
8A  
8B  
9
+125  
-55  
+25  
10  
11  
+125  
-55  
1

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