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MH16S72APHB-7 PDF预览

MH16S72APHB-7

更新时间: 2024-11-29 22:46:15
品牌 Logo 应用领域
三菱 - MITSUBISHI 存储内存集成电路动态存储器时钟
页数 文件大小 规格书
55页 687K
描述
1,207,959,552-BIT (16,777,216 - WORD BY 72-BIT)Synchronous DRAM

MH16S72APHB-7 技术参数

生命周期:Obsolete零件包装代码:DIMM
包装说明:DIMM, DIMM168针数:168
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.36风险等级:5.84
Is Samacsys:N访问模式:SINGLE BANK PAGE BURST
最长访问时间:6 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):100 MHzI/O 类型:COMMON
JESD-30 代码:R-XDMA-N168内存密度:1207959552 bit
内存集成电路类型:SYNCHRONOUS DRAM MODULE内存宽度:72
功能数量:1端口数量:1
端子数量:168字数:16777216 words
字数代码:16000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:16MX72输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:DIMM
封装等效代码:DIMM168封装形状:RECTANGULAR
封装形式:MICROELECTRONIC ASSEMBLY电源:3.3 V
认证状态:Not Qualified刷新周期:4096
自我刷新:YES最大待机电流:0.009 A
子类别:DRAMs最大压摆率:1.44 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子形式:NO LEAD端子节距:1.27 mm
端子位置:DUALBase Number Matches:1

MH16S72APHB-7 数据手册

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Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH16S72APHB -6,-7,-8  
1,207,959,552-BIT (16,777,216 - WORD BY 72-BIT)Synchronous DRAM  
DESCRIPTION  
The MH16S72APHB is 16777216 - word by 72-bit  
Synchronous DRAM module. This consists of nine  
industry standard 16Mx8 Synchronous DRAMs in  
TSOP and one industory standard EEPROM in  
TSSOP.  
The mounting of TSOP on a card edge Dual  
Inline package provides any application where  
high densities and large quantities of memory are  
required.  
85pin  
1pin  
This is a socket type - memory modules, suitable  
for easy interchange or addition of modules.  
94pin  
95pin  
10pin  
11pin  
FEATURES  
CLK Access Time  
Frequency  
(Component SDRAM)  
-6  
-7  
-8  
5.4ns(CL=3)  
6.0ns(CL=2)  
6.0ns(CL=3)  
133MHz  
100MHz  
100MHz  
124pin  
125pin  
40pin  
41pin  
Utilizes industry standard 16M x 8 Sy nchronous DRAMs  
TSOP and industry standard EEPROM in TSSOP  
168-pin (84-pin dual in-line package)  
single 3.3V±0.3V power supply  
Max. Clock frequency -6:133MHz,-7,8:100MHz  
Fully synchronous operation referenced to clock  
rising edge  
4 bank operation controlled by BA0,1(Bank Address)  
/CAS latency- 2/3(programmable)  
Burst length- 1/2/4/8/Full Page(programmable)  
Burst type- sequential / interleave(programmable)  
Column access - random  
84pin  
168pin  
Auto precharge / All bank precharge controlled by A10  
Auto refresh and Self refresh  
4096 refresh cycle /64ms  
LVTTL Interface  
Discrete IC and module design conform to  
PC100/PC133 specification.  
APPLICATION  
PC main memory  
MITSUBISHI  
17.Mar.2000  
MIT-DS-0378-0.1  
ELECTRIC  
( 1 / 55 )  

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