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MH16S72APHB-8 PDF预览

MH16S72APHB-8

更新时间: 2024-11-17 22:46:15
品牌 Logo 应用领域
三菱 - MITSUBISHI 动态存储器
页数 文件大小 规格书
55页 687K
描述
1,207,959,552-BIT (16,777,216 - WORD BY 72-BIT)Synchronous DRAM

MH16S72APHB-8 数据手册

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Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH16S72APHB -6,-7,-8  
1,207,959,552-BIT (16,777,216 - WORD BY 72-BIT)Synchronous DRAM  
DESCRIPTION  
The MH16S72APHB is 16777216 - word by 72-bit  
Synchronous DRAM module. This consists of nine  
industry standard 16Mx8 Synchronous DRAMs in  
TSOP and one industory standard EEPROM in  
TSSOP.  
The mounting of TSOP on a card edge Dual  
Inline package provides any application where  
high densities and large quantities of memory are  
required.  
85pin  
1pin  
This is a socket type - memory modules, suitable  
for easy interchange or addition of modules.  
94pin  
95pin  
10pin  
11pin  
FEATURES  
CLK Access Time  
Frequency  
(Component SDRAM)  
-6  
-7  
-8  
5.4ns(CL=3)  
6.0ns(CL=2)  
6.0ns(CL=3)  
133MHz  
100MHz  
100MHz  
124pin  
125pin  
40pin  
41pin  
Utilizes industry standard 16M x 8 Sy nchronous DRAMs  
TSOP and industry standard EEPROM in TSSOP  
168-pin (84-pin dual in-line package)  
single 3.3V±0.3V power supply  
Max. Clock frequency -6:133MHz,-7,8:100MHz  
Fully synchronous operation referenced to clock  
rising edge  
4 bank operation controlled by BA0,1(Bank Address)  
/CAS latency- 2/3(programmable)  
Burst length- 1/2/4/8/Full Page(programmable)  
Burst type- sequential / interleave(programmable)  
Column access - random  
84pin  
168pin  
Auto precharge / All bank precharge controlled by A10  
Auto refresh and Self refresh  
4096 refresh cycle /64ms  
LVTTL Interface  
Discrete IC and module design conform to  
PC100/PC133 specification.  
APPLICATION  
PC main memory  
MITSUBISHI  
17.Mar.2000  
MIT-DS-0378-0.1  
ELECTRIC  
( 1 / 55 )  

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