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MH16S72PJB-8 PDF预览

MH16S72PJB-8

更新时间: 2024-11-17 22:46:15
品牌 Logo 应用领域
三菱 - MITSUBISHI 存储内存集成电路动态存储器时钟
页数 文件大小 规格书
56页 730K
描述
1207959552-BIT ( 16777216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

MH16S72PJB-8 技术参数

生命周期:Obsolete零件包装代码:DIMM
包装说明:DIMM, DIMM168针数:168
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.36风险等级:5.84
访问模式:FOUR BANK PAGE BURST最长访问时间:6 ns
最大时钟频率 (fCLK):100 MHzI/O 类型:COMMON
JESD-30 代码:R-XDMA-N168内存密度:1207959552 bit
内存集成电路类型:SYNCHRONOUS DRAM MODULE内存宽度:72
功能数量:1端口数量:1
端子数量:168字数:16777216 words
字数代码:16000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:16MX72输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:DIMM
封装等效代码:DIMM168封装形状:RECTANGULAR
封装形式:MICROELECTRONIC ASSEMBLY电源:3.3 V
认证状态:Not Qualified刷新周期:4096
最大待机电流:0.034 A子类别:DRAMs
最大压摆率:1.645 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子形式:NO LEAD
端子节距:1.27 mm端子位置:DUAL
Base Number Matches:1

MH16S72PJB-8 数据手册

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MITSUBISHI LSIs  
MH16S72PJB-7, -8  
1207959552-BIT ( 16777216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM  
PRELIMINARY  
Some of contents are subject to change without notice.  
DESCRIPTION  
The MH16S72PJB is 16777216 - word x 72-bit  
Synchronous DRAM module. This consist of nine industry  
standard 16M x 8 Synchronous DRAMs in TSOP.  
The mounting of TSOP on a card edge dual in-line package  
provides any application where high densities and large of  
quantities memory are required.  
This is a socket-type memory module ,suitable for easy  
interchange or addition of module.  
85pin  
1pin  
FEATURES  
CLK  
Max.  
Frequency  
Access Time  
[component level]  
94pin  
95pin  
10pin  
11pin  
Type name  
MH16S72PJB-7  
MH16S72PJB-8  
100MHz  
100MHz  
6ns (CL = 2, 3)  
6ns (CL = 3)  
Utilizes industry standard 16M X 8 Synchronous DRAMs in  
TSOP package , industry standard Resistered buffer in  
TSSOP package and industry standard PLL in TSSOP  
package  
Single 3.3V +/- 0.3V supply  
LVTTL Interface  
Burst length 1/2/4/8/Full Page(programmable)  
Burst Write / Single Write(programmable)  
Auto precharge / All bank precharge controlled by A10  
Auto refresh and Self refresh  
124pin  
125pin  
40pin  
41pin  
4096 refresh cycles every 64ms  
Discrete IC and module design conform to  
PC/100 specification.  
(module Spec. Rev. 1.0 and SPD 1.2A)  
APPLICATION  
84pin  
168pin  
Main memory unit for computers, Microcomputer memory.  
11/Jan. /1999  
1
MIT-DS-0302-0.0  
MITSUBISHI  
ELECTRIC  

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