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MH16S72VJB-6 PDF预览

MH16S72VJB-6

更新时间: 2024-11-17 22:15:55
品牌 Logo 应用领域
三菱 - MITSUBISHI /
页数 文件大小 规格书
56页 927K
描述
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

MH16S72VJB-6 技术参数

生命周期:Obsolete零件包装代码:DIMM
包装说明:DIMM, DIMM168针数:168
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.36风险等级:5.84
访问模式:FOUR BANK PAGE BURST最长访问时间:5.4 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):133 MHz
I/O 类型:COMMONJESD-30 代码:R-XDMA-N168
内存密度:1207959552 bit内存集成电路类型:SYNCHRONOUS DRAM MODULE
内存宽度:72功能数量:1
端口数量:1端子数量:168
字数:16777216 words字数代码:16000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:16MX72
输出特性:3-STATE封装主体材料:UNSPECIFIED
封装代码:DIMM封装等效代码:DIMM168
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
电源:3.3 V认证状态:Not Qualified
刷新周期:4096自我刷新:YES
最大待机电流:0.043 A子类别:DRAMs
最大压摆率:1.834 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子形式:NO LEAD
端子节距:1.27 mm端子位置:DUAL

MH16S72VJB-6 数据手册

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MITSUBISHI LSIs  
MH16S72VJB-6  
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM  
PRELIMINARY  
Some of contents are subject to change without notice.  
DESCRIPTION  
The MH16S72VJB is 16777216 - word x 72-bit Synchronous  
DRAM module. This consist of eighteen industry standard  
16M x 8 Synchronous DRAMs in TSOP.  
The TSOP on a card edge dual in-line package provides any  
application where high densities and large of quantities  
memory are required.  
85pin  
1pin  
This is a socket-type memory module ,suitable for easy  
interchange or addition of module.  
FEATURES  
Max.  
Frequency  
Access Time from CLK  
[component level]  
94pin  
95pin  
10pin  
11pin  
Type name  
5.4ns  
133MHz  
MH16S72VJB-6  
(CL = 4 at Latch mode)  
Utilizes industry standard 16M X 8 Synchronous DRAMs in  
TSOP package , industry standard Resistered buffer in TSSOP  
package,industry standard PLL in TSSOP package  
Single 3.3V +/- 0.3V supply  
Max.Clock frequency 133MHz  
124pin  
125pin  
40pin  
41pin  
Fully synchronous operation referenced to clock rising edge  
4-bank operation controlled by BA0,BA1(Bank Address)  
/CAS latency -2/3(programmable,at buffer mode)  
LVTTL Interface  
Burst length 1/2/4/8/Full Page(programmable)  
Burst type- Sequential and interleave burst (programmable)  
Random column access  
Burst Write / Single Write(programmable)  
Auto precharge / All bank precharge controlled by A10  
Auto refresh and Self refresh  
4096 refresh cycles every 64ms  
Discrete IC and module design conform to  
PC133 specification.  
APPLICATION  
84pin  
168pin  
Main memory or graphic memory in computer systems  
10/May. /1999  
MIT-DS-0313-0.0  
MITSUBISHI  
ELECTRIC  
1

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