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MH16S72AVJB-6 PDF预览

MH16S72AVJB-6

更新时间: 2024-02-24 02:29:30
品牌 Logo 应用领域
三菱 - MITSUBISHI 存储内存集成电路动态存储器时钟
页数 文件大小 规格书
57页 947K
描述
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

MH16S72AVJB-6 技术参数

生命周期:Obsolete零件包装代码:DIMM
包装说明:DIMM, DIMM168针数:168
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.36风险等级:5.84
Is Samacsys:N访问模式:SINGLE BANK PAGE BURST
最长访问时间:5.4 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):133 MHzI/O 类型:COMMON
JESD-30 代码:R-XDMA-N168内存密度:1207959552 bit
内存集成电路类型:SYNCHRONOUS DRAM MODULE内存宽度:72
功能数量:1端口数量:1
端子数量:168字数:16777216 words
字数代码:16000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:16MX72输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:DIMM
封装等效代码:DIMM168封装形状:RECTANGULAR
封装形式:MICROELECTRONIC ASSEMBLY电源:3.3 V
认证状态:Not Qualified刷新周期:4096
自我刷新:YES最大待机电流:0.209 A
子类别:Other Memory ICs最大压摆率:1.64 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子形式:NO LEAD端子节距:1.27 mm
端子位置:DUALBase Number Matches:1

MH16S72AVJB-6 数据手册

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MITSUBISHI LSIs  
Preliminary Spec.  
Some contents are subject to change without notice.  
MH16S72AVJB-6  
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM  
DESCRIPTION  
The MH16S72AVJB is 16777216 - word x 72-bit Sy nchronous  
DRAM module. This consist of nine industry standard  
16M x 8 Sy nchronous DRAMs in TSOP.  
The TSOP on a card edge dual in-line package prov ides any  
application where high densities and large of quantities memory  
are required.  
85pin  
1pin  
This is a socket-ty pe memory module ,suitable f or easy  
interchange or addition of module.  
FEATURES  
Access Time from CLK  
[component level]  
Max.  
Frequency  
94pin  
95pin  
10pin  
11pin  
Type name  
5.4ns  
MH16S72AVJB-6  
133MHz  
(CL = 4 at Latch mode)  
Utilizes industry standard 16M X 8 Synchronous DRAMs in  
TSOP package , industry standard Resistered buffer in TSSOP  
package,industry standard PLL in TSSOP package  
Single 3.3V +/- 0.3V supply  
Max.Clock frequency 133MHz  
124pin  
125pin  
40pin  
41pin  
Fully synchronous operation referenced to clock rising edge  
4-bank operation controlled by BA0,BA1(Bank Address)  
/CAS latency -2/3(programmable,at buffer mode)  
LVTTL Interface  
Burst length 1/2/4/8/Full Page(programmable)  
Burst type- Sequential and interleave burst (programmable)  
Random column access  
Burst W rite / Single W rite(programmable)  
Auto precharge / All bank precharge controlled by A10  
Auto refresh and Self refresh  
4096 refresh cycles every 64ms  
Discrete IC and module design conform to  
PC133 specification.  
APPLICATION  
84pin  
168pin  
Main memory or graphic memory in computer systems  
MITSUBISHI  
ELECTRIC  
27/Mar. /2001  
MIT-DS-0414-0.1  
1

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