Datasheet > 存储 > SRAM> MCM69P819ZP4

MCM69P819ZP4

更新时间： 2024-11-10 22:09:23

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		存储内存集成电路静态存储器
页数	文件大小	规格书
20页	278K
描述
256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM

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技术参数
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MCM69P819ZP4 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	BGA,
针数：	119	Reach Compliance Code：	unknown
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.53	Is Samacsys：	N
最长访问时间：	4 ns	其他特性：	LINEAR/INTERLEAVED BURST SEQUENCE; INTERNALLY SELF-TIMED WRITE CYCLE; BYTE/GLOBAL WRITE CONTROL
JESD-30 代码：	R-PBGA-B119	JESD-609代码：	e0
长度：	22 mm	内存密度：	4718592 bit
内存集成电路类型：	CACHE SRAM	内存宽度：	18
功能数量：	1	端口数量：	1
端子数量：	119	字数：	262144 words
字数代码：	256000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	256KX18	输出特性：	3-STATE
可输出：	YES	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED	认证状态：	Not Qualified
座面最大高度：	2.4 mm	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	MOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	BALL	端子节距：	1.27 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	14 mm	Base Number Matches：	1

MCM69P819ZP4 数据手册

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by MCM69P819/D

SEMICONDUCTOR TECHNICAL DATA

MCM69P819

256K x 18 Bit Pipelined

BurstRAM Synchronous

Fast Static RAM

The MCM69P819 is a 4M bit synchronous fast static RAM designed to provide

a burstable, high performance, secondary cache for the PowerPC and other

high performance microprocessors. It is organized as 256K words of 18 bits

each. This device integrates input registers, an output register, a 2–bit address

counter, and high speed SRAM onto a single monolithic circuit for reduced parts

count in cache data RAM applications. Synchronous design allows precise cycle

control with the use of an external clock (K).

ZP PACKAGE

PBGA

CASE 999–02

Addresses (SA), data inputs (DQx), and all control signals except output

enable(G) and linear burst order (LBO) are clock (K) controlled through positive–

edge–triggered noninverting registers.

Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst

addresses can be generated internally by the MCM69P819 (burst sequence

operates in linear or interleaved mode dependent upon the state of LBO) and

controlled by the burst address advance (ADV) input pin.

TQ PACKAGE

TQFP

CASE 983A–01

Write cycles are internally self–timed and are initiated by the rising edge of the

clock (K) input. This feature eliminates complex off–chip write pulse generation

and provides increased timing flexibility for incoming signals.

Synchronous byte write (SBx), synchronous global write (SGW), and synchro-

nous write enable (SW) are provided to allow writes to either individual bytes or

to all bytes. The two bytes are designated as “a” and “b”. SBa controls DQa and

SBb controls DQb. Individual bytes are written if the selected byte writes SBx are

asserted with SW. All bytes are written if either SGW is asserted or if all SBx and

SW are asserted.

For read cycles, pipelined SRAMs output data is temporarily stored by an

edge–triggeredoutput register and then released to the output buffers at the next

rising edge of clock (K).

The MCM69P819 operates from a 3.3 V core power supply and all outputs

operate on a 2.5 or 3.3 V power supply. All inputs and outputs are JEDEC stan-

dard JESD8–5 compatible.

•

MCM69P819–3.5: 3.5 ns Access/6 ns Cycle (166 MHz)

MCM69P819–3.8: 3.8 ns Access/6.7 ns Cycle (150 MHz)

MCM69P819–4: 4 ns Access/7.5 ns Cycle (133 MHz)

3.3 V + 10%, – 5% Core Power Supply, 2.5 V or 3.3 V I/O Supply

ADSP, ADSC, and ADV Burst Control Pins

Selectable Burst Sequencing Order (Linear/Interleaved)

Single–Cycle Deselect Timing

Internally Self–Timed Write Cycle

•

Byte Write and Global Write Control

PB1 Version 2.0 Compatible

JEDEC Standard 119–Pin PBGA and 100–Pin TQFP Packages

The PowerPC name is a trademark of IBM Corp., used under license therefrom.

REV 6

1/20/98

Motorola, Inc. 1998

MOTOROLA FAST SRAM

MCM69P819

12 3 4 5 6 7...20

中文翻译

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与MCM69P819ZP4相关器件

型号	品牌	获取价格	描述	数据表
MCM69P819ZP4R	MOTOROLA	获取价格	256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM69Q536	MOTOROLA	获取价格	32K x 36 Bit Synchronous Separate I/O SRAM
MCM69Q536TQ10	MOTOROLA	获取价格	32K x 36 Bit Synchronous Separate I/O SRAM
MCM69Q536TQ10R	MOTOROLA	获取价格	32K x 36 Bit Synchronous Separate I/O SRAM
MCM69Q536TQ6	MOTOROLA	获取价格	32K x 36 Bit Synchronous Separate I/O SRAM
MCM69Q536TQ6R	MOTOROLA	获取价格	32K x 36 Bit Synchronous Separate I/O SRAM
MCM69Q536TQ8	MOTOROLA	获取价格	32K x 36 Bit Synchronous Separate I/O SRAM
MCM69Q536TQ8R	MOTOROLA	获取价格	32K x 36 Bit Synchronous Separate I/O SRAM
MCM69Q618	MOTOROLA	获取价格	64K x 18 Bit Synchronous Separate I/O SRAM
MCM69Q618TQ10	MOTOROLA	获取价格	64K x 18 Bit Synchronous Separate I/O SRAM

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