Datasheet > MCM69R536ZP4.4

MCM69R536ZP4.4

更新时间： 2024-11-12 04:31:27

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		信息通信管理静态存储器
页数	文件大小	规格书
20页	141K
描述
Late-Write SRAM, 32KX36, 2.2ns, BICMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

MCM69R536ZP4.4 数据手册

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document

by MCM69R536/D

MCM69R536

MCM69R618

1M Late Write HSTL

The MCM69R536/618 is a 1M–bit synchronous late write fast static RAM

designed to provide high performance in secondary cache, ATM switch,

Telecom, and other high speed memory applications. The MCM69R618

(organized as 64K words by 18 bits) and the MCM69R536 (organized as 32K

words by 36 bits wide) are fabricated in Motorola’s high performance silicon gate

BiCMOS technology.

The differential clock (CK) inputs control the timing of read/write operations of

theRAM. AttherisingedgeofCK, alladdresses, writeenables, andsynchronous

selects are registered. An internal buffer and special logic enable the memory to

accept write data on the rising edge of CK, a cycle after address and control

signals. Read data is driven on the rising edge of CK.

ZP PACKAGE

PBGA

CASE 999–02

The RAM uses HSTL inputs and outputs. The adjustable input trip–point (V

)

ref

and output voltage (V

) gives the system designer greater flexibility in

DDQ

optimizing system performance.

The synchronous write and byte enables allow writing to individual bytes or the

entire word.

The impedance of the output buffers is programmable allowing the outputs to

match the impedance of the circuit traces which reduces signal reflections.

•

Byte Write Control

Single 3.3 V +10%, –5% Operation

HSTL — I/O (JEDEC Standard JESD8–6 Class 1 Compatible)

HSTL — User Selectable Input Trip–Point

HSTL — Compatible Programmable Impedance Output Drivers

Asynchronous Output Enable

Boundary Scan (JTAG) IEEE 1149.1 Compatible

Differential Clock Inputs

Optional x18 or x36 Organization

MCM69R536/618–4.4 = 4.4 ns

MCM69R536/618–5 = 5 ns

MCM69R536/618–6 = 6 ns

MCM69R536/618–7 = 7 ns

•

119–Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array

(PBGA) Package

REV 2

2/24/00

Motorola, Inc. 2000

MOTOROLA FAST SRAM

MCM69R536•MCM69R618

12 3 4 5 6 7...20

中文翻译

下载PDF

与MCM69R536ZP4.4相关器件

型号	品牌	获取价格	描述	数据表
MCM69R536ZP5	NXP	获取价格	32KX36 LATE-WRITE SRAM, 2.5ns, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119
MCM69R536ZP5R	MOTOROLA	获取价格	Late-Write SRAM, 32KX36, 2.5ns, BICMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-1
MCM69R536ZP6R	MOTOROLA	获取价格	32KX36 LATE-WRITE SRAM, 3ns, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119
MCM69R536ZP7R	MOTOROLA	获取价格	Late-Write SRAM, 32KX36, 3.5ns, BICMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-1
MCM69R537ZP5	MOTOROLA	获取价格	32KX36 CACHE SRAM, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119
MCM69R537ZP5R	MOTOROLA	获取价格	32KX36 CACHE SRAM, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119
MCM69R537ZP6	MOTOROLA	获取价格	32KX36 CACHE SRAM, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119
MCM69R537ZP6R	MOTOROLA	获取价格	32KX36 CACHE SRAM, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119
MCM69R537ZP7	MOTOROLA	获取价格	Cache SRAM, 32KX36, 3.5ns, BICMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119
MCM69R537ZP7R	MOTOROLA	获取价格	32KX36 CACHE SRAM, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119

与MCM69R536ZP4.4相关文章

国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

23
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

7
AMD宣布全球裁员约1000人，调整战略聚焦增长
2024-11-14

8
英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

31

产品中心

服务支持

精选活动

关于我们

帮助中心

MCM69R536ZP4.4

MCM69R536ZP4.4 数据手册

与MCM69R536ZP4.4相关器件

与MCM69R536ZP4.4相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

MCM69R536ZP4.4

MCM69R536ZP4.4 数据手册

与MCM69R536ZP4.4相关器件

与MCM69R536ZP4.4相关文章

您还可以找

您在本页遇到什么问题？