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MCM69R536ZP4.4 PDF预览

MCM69R536ZP4.4

更新时间: 2023-01-02 15:55:17
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 信息通信管理静态存储器
页数 文件大小 规格书
20页 141K
描述
Late-Write SRAM, 32KX36, 2.2ns, BICMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119

MCM69R536ZP4.4 数据手册

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MOTOROLA  
SEMICONDUCTOR TECHNICAL DATA  
Order this document  
by MCM69R536/D  
MCM69R536  
MCM69R618  
1M Late Write HSTL  
The MCM69R536/618 is a 1M–bit synchronous late write fast static RAM  
designed to provide high performance in secondary cache, ATM switch,  
Telecom, and other high speed memory applications. The MCM69R618  
(organized as 64K words by 18 bits) and the MCM69R536 (organized as 32K  
words by 36 bits wide) are fabricated in Motorola’s high performance silicon gate  
BiCMOS technology.  
The differential clock (CK) inputs control the timing of read/write operations of  
theRAM. AttherisingedgeofCK, alladdresses, writeenables, andsynchronous  
selects are registered. An internal buffer and special logic enable the memory to  
accept write data on the rising edge of CK, a cycle after address and control  
signals. Read data is driven on the rising edge of CK.  
ZP PACKAGE  
PBGA  
CASE 999–02  
The RAM uses HSTL inputs and outputs. The adjustable input trip–point (V  
)
ref  
and output voltage (V  
) gives the system designer greater flexibility in  
DDQ  
optimizing system performance.  
The synchronous write and byte enables allow writing to individual bytes or the  
entire word.  
The impedance of the output buffers is programmable allowing the outputs to  
match the impedance of the circuit traces which reduces signal reflections.  
Byte Write Control  
Single 3.3 V +10%, –5% Operation  
HSTL — I/O (JEDEC Standard JESD8–6 Class 1 Compatible)  
HSTL — User Selectable Input Trip–Point  
HSTL — Compatible Programmable Impedance Output Drivers  
Register to Register Synchronous Operation  
Asynchronous Output Enable  
Boundary Scan (JTAG) IEEE 1149.1 Compatible  
Differential Clock Inputs  
Optional x18 or x36 Organization  
MCM69R536/618–4.4 = 4.4 ns  
MCM69R536/618–5 = 5 ns  
MCM69R536/618–6 = 6 ns  
MCM69R536/618–7 = 7 ns  
119–Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array  
(PBGA) Package  
REV 2  
2/24/00  
Motorola, Inc. 2000  

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