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MCM69R536ZP7R PDF预览

MCM69R536ZP7R

更新时间: 2024-11-11 14:43:31
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 信息通信管理静态存储器内存集成电路
页数 文件大小 规格书
20页 141K
描述
Late-Write SRAM, 32KX36, 3.5ns, BICMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119

MCM69R536ZP7R 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:BGA包装说明:BGA, BGA119,7X17,50
针数:119Reach Compliance Code:unknown
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.86Is Samacsys:N
最长访问时间:3.5 ns其他特性:BYTE WRITE CONTROL; BOUNDARY SCAN
I/O 类型:COMMONJESD-30 代码:R-PBGA-B119
JESD-609代码:e0长度:22 mm
内存密度:1179648 bit内存集成电路类型:LATE-WRITE SRAM
内存宽度:36功能数量:1
端口数量:1端子数量:119
字数:32768 words字数代码:32000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:32KX36
输出特性:3-STATE可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA119,7X17,50封装形状:RECTANGULAR
封装形式:GRID ARRAY并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:1.5,3.3 V
认证状态:Not Qualified座面最大高度:2.4 mm
最小待机电流:3.15 V子类别:SRAMs
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3.15 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:BICMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
Base Number Matches:1

MCM69R536ZP7R 数据手册

 浏览型号MCM69R536ZP7R的Datasheet PDF文件第2页浏览型号MCM69R536ZP7R的Datasheet PDF文件第3页浏览型号MCM69R536ZP7R的Datasheet PDF文件第4页浏览型号MCM69R536ZP7R的Datasheet PDF文件第5页浏览型号MCM69R536ZP7R的Datasheet PDF文件第6页浏览型号MCM69R536ZP7R的Datasheet PDF文件第7页 
MOTOROLA  
SEMICONDUCTOR TECHNICAL DATA  
Order this document  
by MCM69R536/D  
MCM69R536  
MCM69R618  
Advance Information  
1M Late Write HSTL  
The MCM69R536/618 is a 1 megabit synchronous late write fast static RAM  
designed to provide high performance in secondary cache, ATM switch,  
Telecom, and other high speed memory applications. The MCM69R618  
organized as 64K words by 18 bits, and the MCM69R536 organized as 32K  
words by 36 bits wide are fabricated in Motorola’s high performance silicon gate  
BiCMOS technology.  
The differential CK clock inputs control the timing of read/write operations of  
the RAM. At the rising edge of the CK clock all addresses, write enables, and  
synchronous selects are registered. An internal buffer and special logic enable  
the memory to accept write data on the rising edge of the CK clock a cycle after  
address and control signals. Read data is driven on the rising edge of the CK  
clock also.  
ZP PACKAGE  
PBGA  
CASE 999–01  
TheRAMusesHSTLinputsandoutputs. Theadjustableinputtrippoint(V  
)
ref  
and output voltage (V  
) gives the system designer greater flexibility in  
DDQ  
optimizing system performance.  
The synchronous write and byte enables allow writing to individual bytes or the  
entire word.  
The impedance of the output buffers is programmable allowing the outputs to  
match the impedance of the circuit traces which reduces signal reflections.  
Byte Write Control  
Single 3.3 V + 10%, – 5% Operation  
HSTL – I/O (JEDEC Standard JESD8–6 Class 1 Compatible)  
HSTL – User Selectable Input Trip–Point  
HSTL – Compatible Programmable Impedance Output Drivers  
Register to Register Synchronous Operation  
Asynchronous Output Enable  
Boundary Scan (JTAG) IEEE 1149.1 Compatible  
Differential Clock Inputs  
Optional x18 or x36 organization  
MCM69R536/618–5 = 5 ns  
MCM69R536/618–6 = 6 ns  
MCM69R536/618–7 = 7 ns  
MCM69R536/618–8 = 8 ns  
119 Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array  
(PBGA) Package  
This document contains information on a new product. Specifications and information herein are subject to change without notice.  
REV 1  
8/15/97  
Motorola, Inc. 1997  

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