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MCM69R618ZP6R PDF预览

MCM69R618ZP6R

更新时间: 2023-01-02 19:00:36
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 信息通信管理静态存储器内存集成电路
页数 文件大小 规格书
20页 141K
描述
64KX18 LATE-WRITE SRAM, 3ns, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119

MCM69R618ZP6R 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119Reach Compliance Code:unknown
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.92最长访问时间:3 ns
其他特性:BYTE WRITE CONTROL; BOUNDARY SCANI/O 类型:COMMON
JESD-30 代码:R-PBGA-B119JESD-609代码:e0
长度:22 mm内存密度:1179648 bit
内存集成电路类型:LATE-WRITE SRAM内存宽度:18
功能数量:1端口数量:1
端子数量:119字数:65536 words
字数代码:64000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:64KX18输出特性:3-STATE
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA119,7X17,50
封装形状:RECTANGULAR封装形式:GRID ARRAY
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:1.5,3.3 V认证状态:Not Qualified
座面最大高度:2.4 mm最小待机电流:3.15 V
子类别:SRAMs最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3.15 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:BICMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mmBase Number Matches:1

MCM69R618ZP6R 数据手册

 浏览型号MCM69R618ZP6R的Datasheet PDF文件第2页浏览型号MCM69R618ZP6R的Datasheet PDF文件第3页浏览型号MCM69R618ZP6R的Datasheet PDF文件第4页浏览型号MCM69R618ZP6R的Datasheet PDF文件第5页浏览型号MCM69R618ZP6R的Datasheet PDF文件第6页浏览型号MCM69R618ZP6R的Datasheet PDF文件第7页 
MOTOROLA  
SEMICONDUCTOR TECHNICAL DATA  
Order this document  
by MCM69R536/D  
MCM69R536  
MCM69R618  
1M Late Write HSTL  
The MCM69R536/618 is a 1M–bit synchronous late write fast static RAM  
designed to provide high performance in secondary cache, ATM switch,  
Telecom, and other high speed memory applications. The MCM69R618  
(organized as 64K words by 18 bits) and the MCM69R536 (organized as 32K  
words by 36 bits wide) are fabricated in Motorola’s high performance silicon gate  
BiCMOS technology.  
The differential clock (CK) inputs control the timing of read/write operations of  
theRAM. AttherisingedgeofCK, alladdresses, writeenables, andsynchronous  
selects are registered. An internal buffer and special logic enable the memory to  
accept write data on the rising edge of CK, a cycle after address and control  
signals. Read data is driven on the rising edge of CK.  
ZP PACKAGE  
PBGA  
CASE 999–02  
The RAM uses HSTL inputs and outputs. The adjustable input trip–point (V  
)
ref  
and output voltage (V  
) gives the system designer greater flexibility in  
DDQ  
optimizing system performance.  
The synchronous write and byte enables allow writing to individual bytes or the  
entire word.  
The impedance of the output buffers is programmable allowing the outputs to  
match the impedance of the circuit traces which reduces signal reflections.  
Byte Write Control  
Single 3.3 V +10%, –5% Operation  
HSTL — I/O (JEDEC Standard JESD8–6 Class 1 Compatible)  
HSTL — User Selectable Input Trip–Point  
HSTL — Compatible Programmable Impedance Output Drivers  
Register to Register Synchronous Operation  
Asynchronous Output Enable  
Boundary Scan (JTAG) IEEE 1149.1 Compatible  
Differential Clock Inputs  
Optional x18 or x36 Organization  
MCM69R536/618–4.4 = 4.4 ns  
MCM69R536/618–5 = 5 ns  
MCM69R536/618–6 = 6 ns  
MCM69R536/618–7 = 7 ns  
119–Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array  
(PBGA) Package  
REV 2  
2/24/00  
Motorola, Inc. 2000  

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