Datasheet > 存储 > SRAM> MCM69Q536TQ10

MCM69Q536TQ10

更新时间： 2024-01-09 19:46:54

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		存储内存集成电路静态存储器
页数	文件大小	规格书
12页	187K
描述
32K x 36 Bit Synchronous Separate I/O SRAM

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技术参数
数据手册

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MCM69Q536TQ10 技术参数

生命周期：	Obsolete	包装说明：	LFQFP,
Reach Compliance Code：	unknown	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.84
Is Samacsys：	N	最长访问时间：	10 ns
其他特性：	SELF TIMED WRITE	JESD-30 代码：	S-PQFP-G176
长度：	24 mm	内存密度：	1179648 bit
内存集成电路类型：	STANDARD SRAM	内存宽度：	36
功能数量：	1	端口数量：	1
端子数量：	176	字数：	32768 words
字数代码：	32000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	32KX36	输出特性：	3-STATE
可输出：	YES	封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH	并行/串行：	PARALLEL
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	MOS	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	宽度：	24 mm
Base Number Matches：	1

MCM69Q536TQ10 数据手册

Order this document

by MCM69Q536/D

SEMICONDUCTOR TECHNICAL DATA

MCM69Q536

Advance Information

32K x 36 Bit Synchronous

Separate I/O SRAM

The Motorola MCM69Q536 is a 1 Megabit static random access memory, organized

as 32K words of 36 bits. It features separate data input and data output buffers and

incorporates input and output registers on board with high speed SRAM.

The MCM69Q536 allows the user to perform transparent writes and data pass

through. Two data bus ports are provided — a data input (D) and a data output (Q) port.

The synchronous design allows for precise cycle control with the use of an external

single clock (K). Address port, data input (D0 – D35), data output (Q0 – Q35), write en-

able (W), chip enables (E1, E2), and pass–through enable (PT) are registered on the

rising edge of clock (K).

TQ PACKAGE

176 LEAD TQFP

CASE 1101–01

Any given cycle operates on only one address. However, for any cycle, reads and

writes can be intermixed. Thus, one can perform a read, a write, or a combination read/

write during any one cycle. For a combination read/write, the contents of the array are

read before the new data is written.

By using the pass–through function, the output port Q can be made to reflect either

the contents of the array or the data presented to the input port D. For read/write or a

read cycle with G low, the Q port will output the contents of the array. However, if PT

is asserted, the Q port will instead output the data presented at the D input port.

•

Single 3.3 V ± 5% Power Supply

Fast Access Times: 6/8/10 ns Max

Sustained Throughput of 2.98 Gigabits/Second

Single Clock Operation

Address, Data Input, E1, E2, PT, W, and Data Output Registers on Chip

83 MHz Maximum Clock Cycle Time

Self Timed Write

Separate Data Input and Data Output Pins

Pass–Through Feature

Asynchronous Output Enable (G)

LVTTL Compatible I/O

No Dead Cycles Required for Reads after Writes or for Writes after Reads

176 Pin TQFP Package

Simultaneous Reads and Writes

Suggested Applications

— ATM

— Ethernet Switches — Routers

— Cell/Frame Buffers — SNA Switches

— Shared Memory

Product Family Configurations

Part

Number

Dual

Address

Single

Address

Dual

I/O

Separate

I/O

MCM69D536

Note 1

Note 2

MCM69D618

MCM69Q536

MCM69Q618

MCM67Q709

MCM67Q909

NOTES:

1. Tie AX and AY address ports together for the part to function as a single address part.

2. Tie GX high for DQX to be inputs and tie WY high and GY low for DQY to be outputs.

This document contains information on a new product. Specifications and information herein are subject to change without notice.

REV 3

11/20/97

Motorola, Inc. 1997

MOTOROLA FAST SRAM

MCM69Q536

12 3 4 5 6 7...12

中文翻译

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与MCM69Q536TQ10相关器件

型号	品牌	获取价格	描述	数据表
MCM69Q536TQ10R	MOTOROLA	获取价格	32K x 36 Bit Synchronous Separate I/O SRAM
MCM69Q536TQ6	MOTOROLA	获取价格	32K x 36 Bit Synchronous Separate I/O SRAM
MCM69Q536TQ6R	MOTOROLA	获取价格	32K x 36 Bit Synchronous Separate I/O SRAM
MCM69Q536TQ8	MOTOROLA	获取价格	32K x 36 Bit Synchronous Separate I/O SRAM
MCM69Q536TQ8R	MOTOROLA	获取价格	32K x 36 Bit Synchronous Separate I/O SRAM
MCM69Q618	MOTOROLA	获取价格	64K x 18 Bit Synchronous Separate I/O SRAM
MCM69Q618TQ10	MOTOROLA	获取价格	64K x 18 Bit Synchronous Separate I/O SRAM
MCM69Q618TQ10R	MOTOROLA	获取价格	64K x 18 Bit Synchronous Separate I/O SRAM
MCM69Q618TQ6	MOTOROLA	获取价格	64K x 18 Bit Synchronous Separate I/O SRAM
MCM69Q618TQ6R	MOTOROLA	获取价格	64K x 18 Bit Synchronous Separate I/O SRAM

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