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MCM69Q618TQ8 PDF预览

MCM69Q618TQ8

更新时间: 2024-01-04 08:49:31
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 存储内存集成电路静态存储器
页数 文件大小 规格书
12页 182K
描述
64K x 18 Bit Synchronous Separate I/O SRAM

MCM69Q618TQ8 技术参数

生命周期:Obsolete包装说明:LQFP,
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.84
最长访问时间:8 ns其他特性:SELF TIMED WRITE
JESD-30 代码:R-PQFP-G100长度:20 mm
内存密度:1179648 bit内存集成电路类型:STANDARD SRAM
内存宽度:18功能数量:1
端口数量:1端子数量:100
字数:65536 words字数代码:64000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:64KX18
输出特性:3-STATE可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:MOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
宽度:14 mmBase Number Matches:1

MCM69Q618TQ8 数据手册

 浏览型号MCM69Q618TQ8的Datasheet PDF文件第2页浏览型号MCM69Q618TQ8的Datasheet PDF文件第3页浏览型号MCM69Q618TQ8的Datasheet PDF文件第4页浏览型号MCM69Q618TQ8的Datasheet PDF文件第5页浏览型号MCM69Q618TQ8的Datasheet PDF文件第6页浏览型号MCM69Q618TQ8的Datasheet PDF文件第7页 
Order this document  
by MCM69Q618/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM69Q618  
Advance Information  
64K x 18 Bit Synchronous  
Separate I/O Fast SRAM  
The Motorola MCM69Q618 is a 1 Megabit static random access memory, organized  
as 64K words of 18 bits. It features separate data input and data output buffers and  
incorporates input and output registers on board with high speed SRAM.  
The MCM69Q618 allows the user to perform transparent write and data pass  
through. Two data bus ports are provided – a data input (D) and a data output (Q) port.  
The synchronous design allows for precise cycle control with the use of an external  
single clock (K). Address port, data input (D0 – D17), data output (Q0 – Q17), write en-  
able (W), chip enables (E1, E2), and pass–through enable (PT) are registered on the  
rising edge of clock (K).  
TQ PACKAGE  
100 PIN TQFP  
CASE 983A–01  
Any given cycle operates on only one address. However, for any cycle, reads and  
writes can be intermixed. Thus, one can perform a read, a write, or a combination read/  
write during any one cycle. For a combination read/write, the contents of the array are  
read before the new data is written.  
By using the pass–through function, the output port Q can be made to reflect either  
the contents of the array or the data presented to the input port D. For read/write or a  
read cycle with G low, the Q port will output the contents of the array. However, if PT  
is asserted, the Q port will instead output the data presented at the D input port.  
Single 3.3 V ± 5% Power Supply  
Fast Access Times: 6/8/10 ns Max  
Sustained Throughput of 1.49 Gigabits/Second  
Single Clock Operation  
Address, Data Input, E1, E2, PT, W, and Data Output Registers on Chip  
83 MHz Maximum Clock Cycle Time  
Self Timed Write  
Separate Data Input and Data Output Pins  
Pass–Through Feature  
Asynchronous Output Enable (G)  
LVTTL Compatible I/O  
No Dead Cycles Required for Reads after Writes or for Writes after Reads  
100 Pin TQFP Package  
Simultaneous Reads and Writes  
Suggested Applications  
— ATM  
— Ethernet Switches — Routers  
— Cell/Frame Buffers — SNA Switches  
— Shared Memory  
Product Family Configurations  
Part  
Number  
Dual  
Address  
Single  
Address  
Dual  
I/O  
Separate  
I/O  
MCM69D536  
Note 1  
Note 1  
Note 2  
Note 2  
MCM69D618  
MCM69Q536  
MCM69Q618  
MCM67Q709  
MCM67Q909  
NOTES:  
1. Tie AX and AY address ports together for the part to function as a single address part.  
2. Tie GX high for DQX to be inputs and tie WY high and GY low for DQY to be outputs.  
This document contains information on a new product. Specifications and information herein are subject to change without notice.  
REV 5  
11/24/97  
Motorola, Inc. 1997  

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