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MCM69C232TQ20 PDF预览

MCM69C232TQ20

更新时间: 2024-11-07 22:20:03
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 存储内存集成电路静态存储器双倍数据速率
页数 文件大小 规格书
20页 252K
描述
4K x 64 CAM

MCM69C232TQ20 技术参数

生命周期:Transferred零件包装代码:QFP
包装说明:LQFP, QFP100,.63X.87针数:100
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.54
Is Samacsys:N最长访问时间:160 ns
JESD-30 代码:R-PQFP-G100JESD-609代码:e0
长度:20 mm内存密度:262144 bit
内存集成电路类型:CONTENT ADDRESSABLE SRAM内存宽度:64
功能数量:1端口数量:1
端子数量:100字数:4096 words
字数代码:4000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:4KX64输出特性:3-STATE
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装等效代码:QFP100,.63X.87
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL电源:3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.2 A子类别:SRAMs
最大压摆率:0.2 mA最大供电电压 (Vsup):3.5 V
最小供电电压 (Vsup):3.1 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:MOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD宽度:14 mm
Base Number Matches:1

MCM69C232TQ20 数据手册

 浏览型号MCM69C232TQ20的Datasheet PDF文件第2页浏览型号MCM69C232TQ20的Datasheet PDF文件第3页浏览型号MCM69C232TQ20的Datasheet PDF文件第4页浏览型号MCM69C232TQ20的Datasheet PDF文件第5页浏览型号MCM69C232TQ20的Datasheet PDF文件第6页浏览型号MCM69C232TQ20的Datasheet PDF文件第7页 
Order this document  
by MCM69C232/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM69C232  
Advance Information  
4K x 64 CAM  
The MCM69C232 is a flexible content–addressable memory (CAM) that can  
contain 4096 entries of 64 bits each. The widths of the match field and the output  
field are programmable, and the match time is designed to be 160 ns. As a result,  
the MCM69C232 is well suited for datacom applications such as Virtual Path  
Identifier/Virtual Circuit Identifier (VPI/VCI) translation in ATM switches up to  
OC12 (622 Mbps) data rates and Media Access Control (MAC) address lookup  
in Ethernet/Fast Ethernet bridges. The match duty cycle of the MCM69C232 is  
user defined, with a trade–off between the time between matches and the num-  
ber of new entries added to the CAM per second.  
TQ PACKAGE  
TQFP  
CASE 983A–01  
4096 Entries  
160 ns Match Time  
Mask Register to “Don’t Care” Selected Bits  
Depth Expansion by Cascading Multiple Devices  
50 MHz Maximum Clock Rate  
Programmable Match and Output Field Widths  
Concurrent Matching of Virtual Path Circuits and Virtual Connection  
Circuits in ATM Mode  
Separate Ports for Control and Match Operations  
200 ns Insertion Time if One of Twelve Entry Queue Locations is Empty  
12 ms Initialization Time After Fast Insertion (at Power–Up Only)  
Single 3.3 V ± 5% Supply  
100 Pin TQFP Package  
IEEE Standard 1149.1 Test Port (JTAG)  
Related Products  
— MCM69D536, MCM69D618 (Dual I/O, Dual Address RAMs)  
— MCM67Q709A, MCM67Q909 (Separate I/O RAMs)  
— MCM69C432 (CAM)  
CONTROL PORT  
MATCH PORT  
12 x 64  
ENTRY QUEUE  
MQ31 – MQ0  
A2 – A0  
DQ15 – DQ0  
STATUS/  
CONTROL  
LOGIC  
4K x 64  
CAM  
TABLE  
K
SEL  
G
WE  
IRQ  
DTACK  
LH/SM  
LL  
MC  
MS  
INPUT REG  
RESET  
VPC  
This document contains information on a new product. Specifications and information herein are subject to change without notice.  
REV 3  
1/15/98  
Motorola, Inc. 1998  

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