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MCM69C233TQ15R PDF预览

MCM69C233TQ15R

更新时间: 2024-11-08 14:53:15
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 双倍数据速率静态存储器内存集成电路
页数 文件大小 规格书
24页 167K
描述
Content Addressable SRAM, 4KX64, 210ns, CMOS, PQFP100, TQFP-100

MCM69C233TQ15R 技术参数

是否Rohs认证:不符合生命周期:Transferred
包装说明:TQFP-100Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.41
风险等级:5.86Is Samacsys:N
最长访问时间:210 ns其他特性:IEEE STANDARD 1149.1 TEST PORT (JTAG)
JESD-30 代码:R-PQFP-G100JESD-609代码:e0
长度:20 mm内存密度:262144 bit
内存集成电路类型:CONTENT ADDRESSABLE SRAM内存宽度:64
功能数量:1端子数量:100
字数:4096 words字数代码:4000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:4KX64
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:QFP100,.63X.87封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE并行/串行:PARALLEL
电源:3.3 V认证状态:Not Qualified
座面最大高度:1.6 mm最大待机电流:0.2 A
子类别:SRAMs最大压摆率:0.2 mA
最大供电电压 (Vsup):3.5 V最小供电电压 (Vsup):3.1 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
宽度:14 mmBase Number Matches:1

MCM69C233TQ15R 数据手册

 浏览型号MCM69C233TQ15R的Datasheet PDF文件第2页浏览型号MCM69C233TQ15R的Datasheet PDF文件第3页浏览型号MCM69C233TQ15R的Datasheet PDF文件第4页浏览型号MCM69C233TQ15R的Datasheet PDF文件第5页浏览型号MCM69C233TQ15R的Datasheet PDF文件第6页浏览型号MCM69C233TQ15R的Datasheet PDF文件第7页 
Order this document  
by MCM69C233/D  
SEMICONDUCTOR TECHNICAL DATA  
MCM69C233  
SCM69C233  
4K x 64 CAM  
The MCM69C233 is a flexible content–addressable memory (CAM) that can  
contain 4096 entries of 64 bits each. The widths of the match field and the output  
field are programmable, and the match time is designed to be 210 ns. As a result,  
the MCM69C233 is well suited for datacom applications such as Virtual Path  
Identifier/Virtual Circuit Identifier (VPI/VCI) translation in ATM switches up to  
OC12 (622 Mbps) data rates and Media Access Control (MAC) address lookup  
in Ethernet/Fast Ethernet bridges. The match duty cycle of the MCM69C233 is  
user defined, with a trade–off between the time between the match request rate  
and the rate of new entries added to the CAM.  
TQ PACKAGE  
TQFP  
CASE 983A–01  
4096 Entries  
210 ns Match Time  
Mask Register to “Don’t Care” Selected Bits  
Depth Expansion by Cascading Multiple Devices  
66 MHz Maximum Clock Rate  
Programmable Match and Output Field Widths  
Concurrent Matching of Virtual Path Circuits and Virtual Connection  
Circuits in ATM Mode  
Separate Ports for Control and Match Operations  
300 ns Insertion Time if 1 of 12 Entry Queue Locations is Empty  
18 ms Initialization Time After Fast Insertion (at Power–Up Only)  
Single 3.3 V ±5% Supply  
IEEE Standard 1149.1 Test Port (JTAG)  
100–Pin TQFP Package  
Related Products  
— MCM69C432, MCM69C232, MCM69C433 (CAMs)  
CONTROL PORT  
MATCH PORT  
12 x 64  
ENTRY QUEUE  
MQ31 – MQ0  
A2 – A0  
DQ15 – DQ0  
STATUS/  
4K x 64  
CAM  
TABLE  
K
G
SEL  
CONTROL  
LOGIC  
LH/SM  
LL  
WE  
IRQ  
DTACK  
MC  
MS  
VPC  
INPUT REG  
RESET  
KMODE  
REV 3  
6/11/01  
Motorola, Inc. 2001  

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