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MC88914D PDF预览

MC88914D

更新时间: 2024-09-17 22:24:07
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 时钟驱动器
页数 文件大小 规格书
4页 81K
描述
LOW SKEW CMOS CLOCK DRIVER WITH RESET

MC88914D 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC88914 is a high–speed, low power, hex divide–by–two D–type  
flip–flop with matched propagation delays, an internal power–on–reset,  
and external synchronous reset. With TTL compatible buffered clock and  
external reset inputs that are common to all flip–flops, the MC88914 is  
ideal for use in high–frequency systems as a clock driver, providing  
multiple outputs that are synchronous.  
LOW SKEW CMOS  
CLOCK DRIVER  
WITH RESET  
Power–on–Reset and External Synchronous Reset  
TTL Compatible Positive Edge–Triggered Clock  
Matched Outputs for Synchronous Applications  
Outputs Source/Sink 24mA  
Part–to–Part Skew of Less Than 3.0ns  
Guaranteed Rise and Fall Times for a Given Capacitive Load  
14  
1
Pinout: 14–Lead Plastic (Top View)  
N SUFFIX  
PLASTIC PACKAGE  
CASE 646–06  
V
GND  
13  
Q
Q
Q
3
SR  
9
GND  
8
CC  
5
4
14  
12  
11  
10  
14  
1
D SUFFIX  
PLASTIC PACKAGE  
CASE 751A–03  
1
2
3
4
5
6
7
V
GND  
Q
Q
Q
2
CLK  
GND  
CC  
0
1
LOGIC DIAGRAM  
SR  
POWER–ON  
RESET  
CLK  
CLK  
D
RST  
Q
CLK  
D
RST  
Q
CLK  
D
RST  
Q
CLK  
D
RST  
Q
CLK  
D
RST  
Q
CLK  
D
RST  
Q
Q
Q
Q
Q
Q
Q
5
0
1
2
3
4
NOTE: This diagram is provided only for understanding of logic operation and should not be used to estimate propagation delays  
8/95  
Motorola, Inc. 1995  
REV 4  
1

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