Datasheet > MC88915TFN55R2

MC88915TFN55R2

更新时间： 2024-11-07 14:53:15

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		驱动输出元件逻辑集成电路
页数	文件大小	规格书
19页	181K
描述
88915 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28, PLASTIC, LCC-28

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MC88915TFN55R2 技术参数

生命周期：	Transferred	零件包装代码：	QLCC
包装说明：	QCCJ,	针数：	28
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.18	其他特性：	MULTIPLE SELECTABLE FREQUENCY RELATIONS FOR THE CLOCK O/PS; O/P FREQUENCY RATIOS ARE 0.5F/1.0F/2.0F
系列：	88915	输入调节：	MUX
JESD-30 代码：	S-PQCC-J28	JESD-609代码：	e0
长度：	11.505 mm	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
功能数量：	1	反相输出次数：	1
端子数量：	28	实输出次数：	7
最高工作温度：	85 °C	最低工作温度：	-40 °C
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.75 ns	座面最大高度：	4.57 mm
最大供电电压 (Vsup)：	5.25 V	最小供电电压 (Vsup)：	4.75 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
宽度：	11.505 mm	最小 fmax：	55 MHz
Base Number Matches：	1

MC88915TFN55R2 数据手册

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SEMICONDUCTOR TECHNICAL DATA

Order Number: MC88915T/D

Rev 5, 08/2001

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The MC88915T Clock Driver utilizes phase–locked loop technology to

lock its low skew outputs’ frequency and phase onto an input reference

clock. It is designed to provide clock distribution for high performance

PC’s and workstations. For a 3.3V version, see the MC88LV915T data

sheet.

The PLL allows the high current, low skew outputs to lock onto a single

clock input and distribute it with essentially zero delay to multiple

components on a board. The PLL also allows the MC88915T to multiply

a low frequency input clock and distribute it locally at a higher (2X) system

frequency. Multiple 88915’s can lock onto a single reference clock, which

is ideal for applications when a central system clock must be distributed

synchronously to multiple boards (see Figure 7).

MC88915T

LOW SKEW CMOS

PLL CLOCK DRIVER

Five “Q” outputs (Q0–Q4) are provided with less than 500 ps skew between their rising edges. The Q5 output is inverted (180°

phase shift) from the “Q” outputs. The 2X_Q output runs at twice the “Q” output frequency, while the Q/2 runs at 1/2 the “Q”

frequency.

The VCO is designed to run optimally between 20 MHz and the 2X_Q F_maxspecification. The wiring diagrams in Figure 5

detail the different feedback configurations which create specific input/output frequency relationships. Possible frequency ratios

of the “Q” outputs to the SYNC input are 2:1, 1:1, and 1:2.

The FREQ_SEL pin provides one bit programmable divide–by in the feedback path of the PLL. It selects between divide–by–1

and divide–by–2 of the VCO before its signal reaches the internal clock distribution section of the chip (see the block diagram on

page 2). In most applications FREQ_SEL should be held high (÷1). If a low frequency reference clock input is used, holding

FREQ_SEL low (÷2) will allow the VCO to run in its optimal range (>20MHz and >40MHz for the TFN133 version).

In normal phase–locked operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the

88915 in a static “test mode”. In this mode there is no frequency limitation on the input clock, which is necessary for a low fre-

quency board test environment. The second SYNC input can be used as a test clock input to further simplify board–level testing

(see detailed description on page 11).

Pulling the OE/RST pin low puts the clock outputs 2X_Q, Q0–Q4, Q5 and Q/2 into a high impedance state (3–state). After the

OE/RST pin goes back high Q0–Q4, Q5 and Q/2 will be reset in the low state, with 2X_Q being the inverse of the selected SYNC

input. Assuming PLL_EN is low, the outputs will remain reset until the 88915 sees a SYNC input pulse.

A lock indicator output (LOCK) will go high when the loop is in steady–state phase and frequency lock. The LOCK output will

go low if phase–lock is lost or when the PLL_EN pin is low. The LOCK output will go high no later than 10ms after the 88915 sees

a SYNC signal and full 5V V_CC

Features

• Five Outputs (Q0–Q4) with Output–Output Skew < 500 ps each being phase and frequency locked to the SYNC input

• The phase variation from part–to–part between the SYNC and FEEDBACK inputs is less than 550 ps (derived from the t_PD

specification, which defines the part–to–part skew)

• Input/Output phase–locked frequency ratios of 1:2, 1:1, and 2:1 are available

• Input frequency range from 5MHz – 2X_Q FMAX spec. (10MHz – 2X_Q FMAX for the TFN133 version)

• Additional outputs available at 2X and +2 the system “Q” frequency. Also a Q (180° phase shift) output available

• All outputs have 36 mA drive (equal high and low) at CMOS levels, and can drive either CMOS or TTL inputs. All inputs

are TTL–level compatible. 88mA I_OL/I_OHspecifications guarantee 50Ω transmission line switching on the incident edge

• Test Mode pin (PLL_EN) provided for low frequency testing. Two selectable CLOCK inputs for test or redundancy pur-

poses. All outputs can go into high impedance (3–state) for board test purposes

• Lock Indicator (LOCK) accuracy indicates a phase–locked state

Yield Surface Modeling and YSM are trademarks of Motorola, Inc.

Rev 5

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

12 3 4 5 6 7...19

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与MC88915TFN55R2相关器件

型号	品牌	获取价格	描述	数据表
MC88915TFN70	MOTOROLA	获取价格	LOW SKEW CMOS PLL CLOCK DRIVER
MC88915TFN70FN	NXP	获取价格	88915 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28, PLAS
MC88915TFN70R2	MOTOROLA	获取价格	88915 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28, PLAS
MC88916	MOTOROLA	获取价格	LOW SKEW CMOS PLL CLOCK DRIVER WITH PROCESSOR RESET
MC88916DW	MOTOROLA	获取价格	LOW SKEW CMOS PLL CLOCK DRIVER WITH PROCESSOR RESET
MC88916DW55	MOTOROLA	获取价格	PLL/Frequency Synthesis Circuit, CMOS, PDSO20
MC88916DW70	IDT	获取价格	88916 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO20, PLAS
MC88916DW70R2	IDT	获取价格	PLL Based Clock Driver, 88916 Series, 5 True Output(s), 1 Inverted Output(s), CMOS, PDSO20
MC88916DW80	MOTOROLA	获取价格	88916 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO20, PLAS
MC88916DW80	IDT	获取价格	PLL Based Clock Driver, 88916 Series, 5 True Output(s), 1 Inverted Output(s), CMOS, PDSO20

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