MC88920DW

更新时间： 2024-11-06 22:46:19

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		时钟驱动器逻辑集成电路光电二极管
页数	文件大小	规格书
10页	120K
描述
LOW SKEW CMOS PLL CLOCK DRIVER With Power-Down/ Power-Up Feature

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MC88920DW 技术参数

生命周期：	Transferred	零件包装代码：	SOIC
包装说明：	SOP, SOP20,.4	针数：	20
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.46	Is Samacsys：	N
其他特性：	O/P FREQUENCY RATIOS ARE 1.0F/2.0F/4.0F; MEETS 68030 & 68040 SKEW REQUIREMENTS	系列：	88920
输入调节：	STANDARD	JESD-30 代码：	R-PDSO-G20
JESD-609代码：	e0	长度：	12.8 mm
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	功能数量：	1
反相输出次数：	1	端子数量：	20
实输出次数：	5	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP20,.4
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
电源：	5 V	传播延迟（tpd）：	3.25 ns
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	1 ns
座面最大高度：	2.65 mm	子类别：	Clock Drivers
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
宽度：	7.5 mm	最小 fmax：	12.5 MHz
Base Number Matches：	1

MC88920DW 数据手册

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SEMICONDUCTOR TECHNICAL DATA

The MC88920 Clock Driver utilizes phase–locked loop technology to

lock its low skew outputs’ frequency and phase onto an input reference

clock. It is designed to provide clock distribution for CISC microprocessor

or single processor RISC systems. The RST_IN/RST_OUT(LOCK) pins

provide a processor reset function designed specifically for the

MC68/EC/LC030/040 microprocessor family.

LOW SKEW CMOS PLL

CLOCK DRIVER

With Power–Down/

Power–Up Feature

The PLL allows the the high current, low skew outputs to lock onto a

single clock input and distribute it with essentially zero delay to multiple

locations on a board. The PLL also allows the MC88920 to multiply a low

frequency input clock and distribute it locally at a higher (2X) system

frequency.

• 2X_Q Output Meets All Requirements of the 20 and 25MHz 68040

Microprocessor PCLK Input Specifications

• Three Outputs (Q0–Q2) With Output–Output Skew <500ps and Six

Outputs Total (Q0–Q2, Q3, 2X_Q,) With <1ns Skew Each Being Phase

and Frequency Locked to the SYNC Input

• The Phase Variation From Part–to–Part Between SYNC and the ‘Q’

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751D–04

Outputs Is Less Than 600ps (Derived From the T

Which Defines the Part–to–Part Skew)

Specification,

• SYNC Input Frequency Range From 5MHZ to 2X_Q F

Max

• Additional Outputs Available at 2X and ÷2 the System ‘Q’ Frequency.

Also a Q (180° Phase Shift) Output Available.

• All Outputs Have ±36mA Drive (Equal High and Low) CMOS Levels. Can Drive Either CMOS or TTL Inputs. All Inputs Are

TTL–Level Compatible

• Test Mode Pin (PLL_EN) Provided for Low Frequency Testing

• Special Power–Down Mode With 2X_Q, Q0, and Q1 Being Reset (With MR), and Other Outputs Remain Running. 2X_Q, Q0

and Q1 Are Guaranteed to Be in Lock 3 Clock Cycles After MR Is Negated

Three ‘Q’ outputs (Q0–Q2) are provided with less than 500ps skew between their rising edges. The Q3 output is inverted (180°

phase shift) from the ‘Q’ outputs. A 2X_Q output runs at twice the ‘Q’ output frequency. The 2X_Q output is ideal for 68040

systems which require a 2X processor clock input, and it meets the tight duty cycle spec of the 20 and 25MHz 68040. The Q/2

output runs at 1/2 the ‘Q’ frequency. This output is fed back internally, providing a fixed 2X multiplication from the ‘Q’ outputs to

the SYNC input. Since the feedback is done internally (no external feedback pin is provided) the input/output frequency

relationships are fixed.

In normal phase–locked operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the

88920 in a static ‘test mode’. In this mode there is no frequency limitation on the input clock, which is necessary for a low

frequency board test environment.

The RST_OUT(LOCK) pin doubles as a phase–lock indicator. When the RST_IN pin is held high, the open drain RST_OUT

pin will be pulled actively low until phase–lock is achieved. When phase–lock occurs, the RST_OUT(LOCK) is released and a

pull–up resistor will pull the signal high. To give a processor reset signal, the RST_IN pin is toggled low, and the

RST_OUT(LOCK) pin will stay low for 1024 cycles of the ‘Q’ output frequency after the RST_IN pin is brought back high.

Description of the RST_IN/RST_OUT(LOCK) Functionality

The RST_IN and RST_OUT(LOCK) pins provide a 68030/040 processor reset function, with the RST_OUT pin also acting as

a lock indicator. If the RST_IN pin is held high during system power–up, the RST_OUT pin will be in the low state until steady

state phase/frequency lock to the input reference is achieved. 1024 ‘Q’ output cycles after phase–lock is achieved the

RST_OUT(LOCK) pin will go into a high impedance state, allowing it to be pulled high by an external pull–up resistor (see the

AC/DC specs for the characteristics of the RST_OUT(LOCK) pin). If the RST_IN pin is held low during power–up, the

RST_OUT(LOCK) pin will remain low.

8/95

REV 2

Motorola, Inc. 1995

12 3 4 5 6 7...10

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与MC88920DW相关器件

型号	品牌	获取价格	描述	数据表
MC88920DWR2	MOTOROLA	获取价格	88920 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO20, PLAS
MC88920DWR2	IDT	获取价格	PLL Based Clock Driver, 88920 Series, 5 True Output(s), 1 Inverted Output(s), CMOS, PDSO20
MC88921	MOTOROLA	获取价格	LOW SKEW CMOS PLL CLOCK DRIVER With Power-Down/ Power-Up Feature
MC88921DW	MOTOROLA	获取价格	LOW SKEW CMOS PLL CLOCK DRIVER With Power-Down/ Power-Up Feature
MC88921DWR2	MOTOROLA	获取价格	88921 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20, PLAS
MC88A	ETC	获取价格	8 TUNES 8 KEY WITH SCAN KEY
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