5秒后页面跳转
捷配首页

Datasheet > MC88915FN55R2
MC88915FN55R2 PDF预览

MC88915FN55R2

更新时间： 2024-09-17 19:35:23
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
14页 291K
描述
PLL Based Clock Driver, 88915 Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PQCC28, PLASTIC, LCC-28

阅读下载

中文翻译

获取价格

MC88915FN55R2 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QLCC包装说明：QCCJ, LDCC28,.5SQ
针数：28Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.63
其他特性：MULTIPLE SELECTABLE FREQUENCY RELATIONS FOR THE CLOCK O/PS; O/P FREQUENCY RATIOS ARE 0.5F/1.0F/2.0F系列：88915
输入调节：MUXJESD-30 代码：S-PQCC-J28
JESD-609代码：e0长度：11.505 mm
逻辑集成电路类型：PLL BASED CLOCK DRIVER最大I（ol）：0.036 A
湿度敏感等级：1功能数量：1
反相输出次数：1端子数量：28
实输出次数：7最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC28,.5SQ
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：220电源：5 V
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.75 ns
座面最大高度：4.57 mm子类别：Clock Drivers
最大供电电压 (Vsup)：5.25 V最小供电电压 (Vsup)：4.75 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn85Pb15)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：11.505 mm
最小 fmax：55 MHzBase Number Matches：1

MC88915FN55R2 数据手册

 浏览型号MC88915FN55R2的Datasheet PDF文件第2页浏览型号MC88915FN55R2的Datasheet PDF文件第3页浏览型号MC88915FN55R2的Datasheet PDF文件第4页浏览型号MC88915FN55R2的Datasheet PDF文件第5页浏览型号MC88915FN55R2的Datasheet PDF文件第6页浏览型号MC88915FN55R2的Datasheet PDF文件第7页 
MC88915  
Low Skew CMOS PLL Clock Drivers  
The MC88915 Clock Driver utilizes phase-locked loop technology to lock its low skew  
outputs' frequency and phase onto an input reference clock. It is designed to provide clock  
distribution for high performance PC's and workstations.  
MC88915  
The PLL allows the high current, low skew outputs to lock onto a single clock input and  
distribute it to multiple components on a board. The PLL also allows the MC88915 to  
multiply a low frequency input clock and distribute it locally at a higher (2X) system  
frequency. Multiple 88915's can lock onto a single reference clock, which is ideal for  
applications when a central system clock must be distributed synchronously to multiple  
boards (see Figure 9).  
LOW SKEW CMOS PLL  
CLOCK DRIVER  
Five “Q” outputs (QO-Q4) are provided with less than 500 ps skew between their rising  
edges. The Q5 output is inverted (180° phase shift) from the “Q” outputs. The 2X_Q output  
runs at twice the “Q” output frequency, while the Q/2 runs at 1/2 the “Q” frequency.  
The VCO is designed to run optimally between 20 MHz and the 2X_Q Fmax  
specification. The wiring diagrams in Figure 5 detail the different feedback configurations  
which create specific input/output frequency relationships. Possible frequency ratios of the  
“Q” outputs to the SYNC input are 2:1, 1:1, and 1:2.  
The FREQ_SEL pin provides one bit programmable divide-by in the feedback path of  
the PLL. It selects between divide-by-1 and divide-by-2 of the VCO before its signal  
reaches the internal clock distribution section of the chip (see the block diagram on page  
2). In most applications FREQ_SEL should be held high (÷1). If a low frequency reference  
clock input is used, holding FREQ_SEL low (÷2) will allow the VCO to run in its optimal  
range (>20 MHz).  
FN SUFFIX  
28-LEAD PLCC PACKAGE  
CASE 776-02  
In normal phase-locked operation, the PLL_EN pin is held high. Pulling the PLL_EN pin  
low disables the VCO and puts the 88915 in a static “test mode”. In this mode there is no  
frequency limitation on the input clock, which is necessary for a low frequency board test  
environment. The second SYNC input can be used as a test clock input to further simplify  
board-level testing (see detailed description on page 11).  
A lock indicator output (LOCK) will go high when the loop is in steady-state phase and  
frequency lock. The LOCK output will go low if phase-lock is lost or when the PLL_EN pin  
is low. Under certain conditions the lock output may remain low, even though the part is  
phase-locked. Therefore, the LOCK output signal should not be used to drive any active  
circuitry; it should be used for passive monitoring or evaluation purposes only.  
EI SUFFIX  
28-LEAD PLCC PACKAGE  
Pb-FREE PACKAGE  
CASE 776-02  
Features  
•
•
Five outputs (Q0–Q4) with output-output skew < 500 ps, each being phase and frequency locked to the SYNC input  
The phase variation from part-to-part between the SYNC and FEEDBACK inputs is less than 550 ps (derived from the tPD specification,  
defining the part-to-part skew).  
•
•
•
•
Input/output phase-locked frequency ratios of 1:2, 1:1, and 2:1 are available  
Input frequency range from 5 MHz – 2X_Q fmax specification  
Additional outputs available at 2X and +2 the system “Q” frequency. Also, a Q (180° phase shift) output available  
All outputs have ±36 mA drive (equal high and low) at CMOS levels, and can drive either CMOS or TTL inputs. All inputs are  
TTL-level compatible.  
•
•
Test mode pin (PLL_EN) provided for low frequency testing. Two selectable CLOCK inputs for test or redundancy purposes.  
28-lead Pb-free package available.  
IDT™ / ICS™ CMOS PLL CLOCK DRIVERS  
1
MC88915 REV 6 JULY 10, 2007  
1234567...14

中文翻译

下载PDF

MC88915FN55R2 替代型号

型号 品牌 替代类型 描述 数据表
9DB102BGLFT IDT

功能相似

 Two Output Differential Buffer for PCIe Gen1 & Gen2

与MC88915FN55R2相关器件

型号 品牌 获取价格 描述 数据表
MC88915FN70 MOTOROLA

获取价格

 		88915 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28, PLAS
MC88915FN70PLCC MOTOROLA

获取价格

 		Low Skew CMOS PLL Clock Driver
MC88915FN70R2 MOTOROLA

获取价格

 		88915 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28, PLAS
MC88915T MOTOROLA

获取价格

 		LOW SKEW CMOS PLL CLOCK DRIVER
MC88915TFN100 NXP

获取价格

 		88915 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28, PLAS
MC88915TFN100 MOTOROLA

获取价格

 		LOW SKEW CMOS PLL CLOCK DRIVER
MC88915TFN100FN NXP

获取价格

 		IC 88915 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28, P
MC88915TFN100R2 MOTOROLA

获取价格

 		PLL Based Clock Driver, 88915 Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PQCC28
MC88915TFN100R2 IDT

获取价格

 		PLL Based Clock Driver, 88915 Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PQCC28
MC88915TFN133 MOTOROLA

获取价格

 		LOW SKEW CMOS PLL CLOCK DRIVER

与MC88915FN55R2相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证