5秒后页面跳转
捷配首页

Datasheet > MC88915TFN160FN
MC88915TFN160FN PDF预览

MC88915TFN160FN

更新时间： 2024-11-07 14:53:15
品牌 Logo 应用领域
恩智浦 - NXP 驱动输出元件逻辑集成电路
页数 文件大小 规格书
18页 238K
描述
88915 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28, PLASTIC, LCC-28

阅读下载

中文翻译

获取价格

MC88915TFN160FN 技术参数

生命周期：Obsolete零件包装代码：QLCC
包装说明：QCCJ,针数：28
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.84其他特性：MULTIPLE SELECTABLE FREQUENCY RELATIONS FOR THE CLOCK O/PS; O/P FREQUENCY RATIOS ARE 0.5F/1.0F/2.0F
系列：88915输入调节：MUX
JESD-30 代码：S-PQCC-J28长度：11.505 mm
逻辑集成电路类型：PLL BASED CLOCK DRIVER功能数量：1
反相输出次数：1端子数量：28
实输出次数：7最高工作温度：70 °C
最低工作温度：输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装形状：SQUARE封装形式：CHIP CARRIER
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.75 ns
座面最大高度：4.57 mm最大供电电压 (Vsup)：5.25 V
最小供电电压 (Vsup)：4.75 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
宽度：11.505 mm最小 fmax：160 MHz
Base Number Matches：1

MC88915TFN160FN 数据手册

 浏览型号MC88915TFN160FN的Datasheet PDF文件第2页浏览型号MC88915TFN160FN的Datasheet PDF文件第3页浏览型号MC88915TFN160FN的Datasheet PDF文件第4页浏览型号MC88915TFN160FN的Datasheet PDF文件第5页浏览型号MC88915TFN160FN的Datasheet PDF文件第6页浏览型号MC88915TFN160FN的Datasheet PDF文件第7页 
Freescale Semiconductor, Inc.  
TECHNICAL DATA  
Order number: MC88915T  
Rev 6, 08/2004  
MC88915TFN55  
Low Skew CMOS PLL Clock Drivers,  
MC88915TFN70  
MC88915TFN100  
MC88915TFN133  
MC88915TFN160  
3-State  
55, 70, 100, 133, and 160 MHz Versions  
The MC88915T Clock Driver utilizes phase-locked loop (PLL) technology to  
lock its low skew outputs frequencies and phase onto an input reference clock.  
It is designed to provide clock distribution for high performance PCs and  
workstations. For a 3.3 V version, see the MC88LV915T data sheet.  
The PLL allows the high current, low skew outputs to lock onto a single  
clock input and distribute it with essentially zero delay to multiple components  
on a board. The PLL also allows the MC88915T to multiply a low frequency  
input clock and distribute it locally at a higher (2X) system frequency. Multiple  
88915s can lock onto a single reference clock, ideal for applications when a  
central system clock must be distributed synchronously to multiple boards  
(see Figure 9).  
LOW SKEW CMOS  
PLL CLOCK DRIVER  
Five “Q” outputs (Q0–Q4) are provided with less than 500 ps skew between  
their rising edges. The Q5 output is inverted (180° phase shift) from the “Q”  
outputs. The 2X_Q output runs at twice the “Q” output frequency, while the  
Q/2 runs at 1/2 the “Q” frequency.  
The VCO is designed to run optimally between 20 MHz and the 2X_Q fmax  
specification. The wiring diagrams in Figure 7 detail the different feedback  
configurations, creating specific input/output frequency relationships. Possible  
frequency ratios of the “Q” outputs to the SYNC input are 2:1, 1:1, and 1:2.  
The FREQ_SEL pin provides one bit programmable divide-by in the feed-  
back path of the PLL. It selects between divide-by-1 and divide-by-2 of the VCO  
FN SUFFIX  
28-LEAD PLCC PACKAGE  
CASE 776-02  
before its signal reaches the internal clock distribution section of the chip (see Figure 2. MC88915T Block Diagram (All Versions)). In  
most applications FREQ_SEL should be held high (÷1). If a low frequency reference clock input is used, holding FREQ_SEL low (÷2)  
allows the VCO to run in its optimal range (>20 MHz and >40 MHz for the TFN133 version).  
In normal phase-locked operation the PLL_EN pi is held high. Pulling the PLL_EN pin low disables the VCO and puts the 88915  
in a static “test mode.” In this mode, there is no frequency limitation on the input clock, necessary for a low frequency board test en-  
vironment. The second SYNC input can be used as a test clock input to further simplify board-level testing (see APPLICATIONS IN-  
FORMATION FOR ALL VERSIONS).  
Pulling the OE/RST pin low puts the clock outputs 2X_Q, Q0–Q4, Q5, and Q/2 into a high impedance state (3-state). After the  
OE/RST pin goes back high Q0–Q4, Q5, and Q/2 will be reset in the low state, with 2X_Q being the inverse of the selected SYNC  
input. Assuming PLL_EN is low, the outputs will remain reset until the 88915 sees a SYNC input pulse.  
A lock indicator output (LOCK) will go high when the loop is in steady-state phase and frequency lock. The LOCK output will go  
low if phase-lock is lost, or when the PLL_EN pin is low. The LOCK output will go high no later than 10 ms after the 88915 sees a  
SYNC signal and full 5.0 V VCC  
.
Features  
•
•
Five outputs (Q0–Q4) with output-output skew < 500 ps, each being phase and frequency locked to the SYNC input  
The phase variation from part-to-part between the SYNC and FEEDBACK inputs is less than 550 ps (derived from the tPD  
specification, defining the part-to-part skew).  
•
•
•
•
Input/output phase-locked frequency ratios of 1:2, 1:1, and 2:1 are available  
Input frequency range from 5 MHz – 2X_Q fmax specification (10 MHz – 2X_Q fmax for the TFN133 version)  
Additional outputs available at 2X and +2 the system “Q” frequency. Also, a Q (180° phase shift) output available  
All outputs have ±36 mA drive (equal high and low) at CMOS levels, and can drive either CMOS or TTL inputs. All inputs are  
TTL-level compatible. ±88 mA IOL/IOH specifications guarantee 50 Ω transmission line switching on the incident edge.  
Test mode pin (PLL_EN) provided for low frequency testing. Two selectable CLOCK inputs for test or redundancy purposes. All  
outputs can go into high impedance (3-state) for board test purposes.  
•
•
Lock indicator (LOCK) accuracy indicates a phase-locked state  
Yield Surface Modeling and YSM are trademarks of Motorola, Inc.  
26  
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA  
1234567...18

中文翻译

下载PDF

与MC88915TFN160FN相关器件

型号 品牌 获取价格 描述 数据表
MC88915TFN160R2 MOTOROLA

获取价格

 		PLL Based Clock Driver, 88915 Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PQCC28
MC88915TFN55 MOTOROLA

获取价格

 		LOW SKEW CMOS PLL CLOCK DRIVER
MC88915TFN55 NXP

获取价格

 		88915 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28, PLAS
MC88915TFN55FN NXP

获取价格

 		IC 88915 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28, P
MC88915TFN55R2 MOTOROLA

获取价格

 		88915 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28, PLAS
MC88915TFN55R2 IDT

获取价格

 		PLL Based Clock Driver, 88915 Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PQCC28
MC88915TFN55R2 NXP

获取价格

 		IC,1:8 OUTPUT,CMOS,LDCC,28PIN,PLASTIC
MC88915TFN70 MOTOROLA

获取价格

 		LOW SKEW CMOS PLL CLOCK DRIVER
MC88915TFN70FN NXP

获取价格

 		88915 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28, PLAS
MC88915TFN70R2 MOTOROLA

获取价格

 		88915 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28, PLAS

与MC88915TFN160FN相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证