MC74VHC1GT32
2−Input OR Gate/CMOS
Logic Level Shifter
The MC74VHC1GT32 is an advanced high speed CMOS 2−input
OR gate fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL
while maintaining CMOS low power dissipation.
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The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The device input is compatible with TTL−type input thresholds and
the output has a full 5 V CMOS level output swing. The input protection
circuitry on this device allows overvoltage tolerance on the input,
allowing the device to be used as a logic−level translator from 3 V
CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V
CMOS Logic while operating at the high−voltage power supply.
The MC74VHC1GT32 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHC1GT32 to be used to interface 5 V circuits to
3 V circuits. The output structures also provide protection when
MARKING
DIAGRAMS
5
5
VN M G
1
G
SC−88A/SC70−5/SOT−353
DF SUFFIX
1
5
CASE 419A
5
VN M G
G
V
CC
= 0 V. These input and output structures help prevent device
1
destruction caused by supply voltage − input/output voltage mismatch,
battery backup, hot insertion, etc.
1
TSOP−5/SOT23−5/SC59−5
DT SUFFIX
CASE 483
Features
• High Speed: t = 3.5 ns (Typ) at V = 5 V
PD
CC
VN
M
G
= Device Code
= Date Code*
= Pb−Free Package
• Low Power Dissipation: I = 2 mA (Max) at T = 25°C
CC
A
• TTL−Compatible Inputs: V = 0.8 V; V = 2 V
IL
IH
(Note: Microdot may be in either location)
*Date Code orientation and/or position may vary
depending upon manufacturing location.
• CMOS−Compatible Outputs: V > 0.8 V ; V < 0.1 V @Load
OH
CC
OL
CC
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
• Pin and Function Compatible with Other Standard Logic Families
• Chip Complexity: FETs = 65; Equivalent Gates = 15
• Pb−Free Packages are Available
PIN ASSIGNMENT
1
2
3
4
5
IN B
IN A
GND
OUT Y
V
CC
5
V
1
2
IN B
IN A
GND
CC
FUNCTION TABLE
Inputs
Output
Y
A
B
4
OUT Y
3
L
L
L
H
L
L
H
H
H
Figure 1. Pinout (Top View)
H
H
H
IN A
IN B
≥ 1
OUT Y
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
Figure 2. Logic Symbol
© Semiconductor Components Industries, LLC, 2007
1
Publication Order Number:
February, 2007 − Rev. 10
MC74VHC1GT32/D