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MC74VHC1GT50DFR2 PDF预览

MC74VHC1GT50DFR2

更新时间: 2024-10-29 15:45:23
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 输入元件光电二极管逻辑集成电路
页数 文件大小 规格书
12页 216K
描述
AHC/VHC SERIES, 1-INPUT NON-INVERT GATE, PDSO5, SC-70, SC-88A, SOT-353, 5 PIN

MC74VHC1GT50DFR2 技术参数

生命周期:Transferred零件包装代码:SOT-353
包装说明:TSSOP,针数:5
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.28系列:AHC/VHC
JESD-30 代码:R-PDSO-G5长度:2 mm
逻辑集成电路类型:BUFFER功能数量:1
输入次数:1端子数量:5
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟(tpd):9.5 ns认证状态:Not Qualified
座面最大高度:1.1 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
宽度:1.25 mmBase Number Matches:1

MC74VHC1GT50DFR2 数据手册

 浏览型号MC74VHC1GT50DFR2的Datasheet PDF文件第2页浏览型号MC74VHC1GT50DFR2的Datasheet PDF文件第3页浏览型号MC74VHC1GT50DFR2的Datasheet PDF文件第4页浏览型号MC74VHC1GT50DFR2的Datasheet PDF文件第5页浏览型号MC74VHC1GT50DFR2的Datasheet PDF文件第6页浏览型号MC74VHC1GT50DFR2的Datasheet PDF文件第7页 
with LSTTL–Compatible Inputs  
The MC74VHC1GT50 is a single gate noninverting buffer  
fabricated with silicon gate CMOS technology. It achieves high speed  
operation similar to equivalent Bipolar Schottky TTL while  
maintaining CMOS low power dissipation.  
http://onsemi.com  
The internal circuit is composed of three stages, including a buffer  
output which provides high noise immunity and stable output.  
The device input is compatible with TTL–type input thresholds and  
the output has a full 5V CMOS level output swing. The input  
protection circuitry on this device allows overvoltage tolerance on the  
input, allowing the device to be used as a logic–level translator from  
3.0V CMOS logic to 5.0V CMOS Logic or from 1.8V CMOS logic to  
3.0V CMOS Logic while operating at the high–voltage power supply.  
The MC74VHC1GT50 input structure provides protection when  
voltages up to 7V are applied, regardless of the supply voltage. This  
allows the MC74VHC1GT50 to be used to interface 5V circuits to 3V  
MARKING DIAGRAM  
SC–88A / SOT–353/SC–70  
DF SUFFIX  
d
VL  
CASE 419A  
Pin 1  
d = Date Code  
TSOP–5/SOT–23/SC–59  
DT SUFFIX  
d
VL  
circuits. The output structures also provide protection when V  
= 0V.  
CC  
CASE 483A  
These input and output structures help prevent device destruction  
caused by supply voltage – input/output voltage mismatch, battery  
backup, hot insertion, etc.  
Pin 1  
d = Date Code  
High Speed: t  
= 3.5ns (Typ) at V  
= 5V  
PD  
Low Power Dissipation: I  
CC  
= 2µA (Max) at T = 25°C  
CC  
A
PIN ASSIGNMENT  
TTL–Compatible Inputs: V = 0.8V; V = 2.0V  
IL  
IH  
1
2
3
4
5
NC  
IN A  
GND  
CMOS–CompatibleOutputs: V  
> 0.8V ; V < 0.1V @Load  
OH  
CC OL CC  
Power Down Protection Provided on Inputs and Outputs  
Balanced Propagation Delays  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300mA  
OUT Y  
VCC  
ESD Performance: HBM > 1500V; MM > 200V  
NC  
IN A  
GND  
VCC  
1
2
3
5
4
ORDERING INFORMATION  
Seedetailedorderingandshippinginformationinthepackage  
dimensions section on page 4 of this data sheet.  
OUT Y  
Figure 1. 5–Lead SOT–353 Pinout (Top View)  
FUNCTION TABLE  
LOGIC SYMBOL  
A Input  
Y Output  
1
L
L
IN A  
OUT Y  
H
H
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
June, 2000 – Rev. 2  
MC74VHC1GT50/D  

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