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MC74VHC1GT32DF1G PDF预览

MC74VHC1GT32DF1G

更新时间: 2024-11-04 12:05:07
品牌 Logo 应用领域
安森美 - ONSEMI 转换器电平转换器
页数 文件大小 规格书
6页 129K
描述
2-Input OR Gate/CMOS Logic Level Shifter

MC74VHC1GT32DF1G 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOT-353包装说明:TSSOP, TSSOP5/6,.08
针数:5Reach Compliance Code:compliant
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:5.34系列:AHC/VHC
JESD-30 代码:R-PDSO-G5JESD-609代码:e3
长度:2 mm负载电容(CL):50 pF
逻辑集成电路类型:OR GATE最大I(ol):0.008 A
湿度敏感等级:1功能数量:1
输入次数:2端子数量:5
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP5/6,.08封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:3.3/5 V
Prop。Delay @ Nom-Sup:10 ns传播延迟(tpd):15.5 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:1.1 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin (Sn)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:1.25 mm
Base Number Matches:1

MC74VHC1GT32DF1G 数据手册

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MC74VHC1GT32  
2-Input OR Gate/CMOS  
Logic Level Shifter  
The MC74VHC1GT32 is an advanced high speed CMOS 2input  
OR gate fabricated with silicon gate CMOS technology. It achieves  
high speed operation similar to equivalent Bipolar Schottky TTL  
while maintaining CMOS low power dissipation.  
http://onsemi.com  
The internal circuit is composed of three stages, including a buffer  
output which provides high noise immunity and stable output.  
The device input is compatible with TTLtype input thresholds and  
the output has a full 5 V CMOS level output swing. The input protection  
circuitry on this device allows overvoltage tolerance on the input,  
allowing the device to be used as a logiclevel translator from 3 V  
CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V  
CMOS Logic while operating at the highvoltage power supply.  
The MC74VHC1GT32 input structure provides protection when  
voltages up to 7 V are applied, regardless of the supply voltage. This  
allows the MC74VHC1GT32 to be used to interface 5 V circuits to  
3 V circuits. The output structures also provide protection when  
MARKING  
DIAGRAMS  
5
5
VN M G  
1
G
SC88A / SC705 / SOT353  
DF SUFFIX  
1
5
CASE 419A  
5
VN M G  
G
V
CC  
= 0 V. These input and output structures help prevent device  
1
destruction caused by supply voltage input/output voltage mismatch,  
battery backup, hot insertion, etc.  
1
TSOP5 / SOT235 / SC595  
DT SUFFIX  
CASE 483  
Features  
High Speed: t = 3.5 ns (Typ) at V = 5 V  
PD  
CC  
VN  
M
G
= Device Code  
= Date Code*  
= PbFree Package  
Low Power Dissipation: I = 2 mA (Max) at T = 25°C  
CC  
A
TTLCompatible Inputs: V = 0.8 V; V = 2 V  
IL  
IH  
(Note: Microdot may be in either location)  
*Date Code orientation and/or position may vary  
depending upon manufacturing location.  
CMOSCompatible Outputs: V > 0.8 V ; V < 0.1 V @Load  
OH  
CC  
OL  
CC  
Power Down Protection Provided on Inputs and Outputs  
Balanced Propagation Delays  
Pin and Function Compatible with Other Standard Logic Families  
Chip Complexity: FETs = 65; Equivalent Gates = 15  
PIN ASSIGNMENT  
1
2
3
4
5
IN B  
IN A  
NLV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AECQ100  
Qualified and PPAP Capable  
These Devices are PbFree and are RoHS Compliant  
GND  
OUT Y  
V
CC  
5
V
1
IN B  
IN A  
GND  
CC  
FUNCTION TABLE  
2
Inputs  
Output  
Y
A
B
L
L
L
H
L
L
H
H
H
4
OUT Y  
3
H
H
Figure 1. Pinout (Top View)  
1  
H
IN A  
IN B  
OUT Y  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
Figure 2. Logic Symbol  
© Semiconductor Components Industries, LLC, 2013  
1
Publication Order Number:  
July, 2013 Rev. 12  
MC74VHC1GT32/D  

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