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MC74HC175AD PDF预览

MC74HC175AD

更新时间: 2024-11-01 23:05:47
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 248K
描述
Quad D Flip=Flop with Common Clck and Reset

MC74HC175AD 技术参数

生命周期:Transferred零件包装代码:SOIC
包装说明:SOP, SOP16,.25针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.24Is Samacsys:N
系列:HC/UHJESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:9.9 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:6000000 Hz最大I(ol):0.0024 A
位数:4功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE电源:2/6 V
传播延迟(tpd):32 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:FF/Latches
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
触发器类型:POSITIVE EDGE宽度:3.9 mm
最小 fmax:25 MHzBase Number Matches:1

MC74HC175AD 数据手册

 浏览型号MC74HC175AD的Datasheet PDF文件第2页浏览型号MC74HC175AD的Datasheet PDF文件第3页浏览型号MC74HC175AD的Datasheet PDF文件第4页浏览型号MC74HC175AD的Datasheet PDF文件第5页浏览型号MC74HC175AD的Datasheet PDF文件第6页浏览型号MC74HC175AD的Datasheet PDF文件第7页 
SEMICONDUCTOR TECHNICAL DATA  
J SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
High–Performance Silicon–Gate CMOS  
16  
1
The MC54/74HC175A is identical in pinout to the LS175. The device  
inputs are compatible with standard CMOS outputs; with pullup resistors,  
they are compatible with LSTTL outputs.  
This device consists of four D flip–flops with common Reset and Clock  
inputs, and separate D inputs. Reset (active–low) is asynchronous and  
occurs when a low level is applied to the Reset input. Information at a D input  
is transferred to the corresponding Q output on the next positive going edge  
of the Clock input.  
N SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
16  
1
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
D SUFFIX  
SOIC PACKAGE  
CASE 751B–05  
16  
1
1
Low Input Current: 1 µA  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
DT SUFFIX  
TSSOP PACKAGE  
CASE 948F–01  
16  
Chip Complexity 166 FETs or 41.5 Equivalent Gates  
ORDERING INFORMATION  
MC54HCXXXAJ  
Ceramic  
Plastic  
SOIC  
LOGIC DIAGRAM  
MC74HCXXXAN  
MC74HCXXXAD  
MC74HCXXXADT  
9
2
3
TSSOP  
CLOCK  
Q0  
Q0  
7
6
10  
Q1  
Q1  
Q2  
INVERTING  
AND  
NONINVERTING  
OUTPUTS  
4
5
D0  
D1  
PIN ASSIGNMENT  
DATA  
INPUTS  
11  
15  
14  
Q2  
Q3  
Q3  
12  
13  
D2  
D3  
RESET  
Q0  
1
2
16  
15  
V
CC  
Q3  
Q0  
D0  
3
4
5
6
7
8
14  
13  
12  
11  
10  
9
Q3  
1
RESET  
D3  
PIN 16 = V  
CC  
PIN 8 = GND  
D1  
D2  
Q1  
Q2  
Q1  
Q2  
GND  
CLOCK  
FUNCTION TABLE  
Inputs  
Reset Clock  
Outputs  
D
Q
Q
L
H
H
H
X
X
H
L
L
H
L
H
L
H
L
X
No Change  
This document contains information on a product under development. Motorola reserves the right to  
change or discontinue this product without notice.  
10/95  
REV 0  
Motorola, Inc. 1995  

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