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MC74HC175AN PDF预览

MC74HC175AN

更新时间: 2024-10-31 23:05:47
品牌 Logo 应用领域
安森美 - ONSEMI 触发器逻辑集成电路光电二极管时钟
页数 文件大小 规格书
8页 194K
描述
Quad D Flip-Flop with Common Clock and Reset

MC74HC175AN 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:7.22系列:HC/UH
JESD-30 代码:R-PDIP-T16JESD-609代码:e0
长度:19.175 mm负载电容(CL):50 pF
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:20000000 Hz
最大I(ol):0.004 A位数:4
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
包装方法:RAIL峰值回流温度(摄氏度):235
电源:2/6 V传播延迟(tpd):225 ns
认证状态:Not Qualified座面最大高度:4.44 mm
子类别:FF/Latches最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:7.62 mm
最小 fmax:24 MHz

MC74HC175AN 数据手册

 浏览型号MC74HC175AN的Datasheet PDF文件第2页浏览型号MC74HC175AN的Datasheet PDF文件第3页浏览型号MC74HC175AN的Datasheet PDF文件第4页浏览型号MC74HC175AN的Datasheet PDF文件第5页浏览型号MC74HC175AN的Datasheet PDF文件第6页浏览型号MC74HC175AN的Datasheet PDF文件第7页 
High–Performance Silicon–Gate CMOS  
The MC74HC175A is identical in pinout to the LS175. The device  
inputs are compatible with standard CMOS outputs; with pullup  
resistors, they are compatible with LSTTL outputs.  
http://onsemi.com  
This device consists of four D flip–flops with common Reset and  
Clock inputs, and separate D inputs. Reset (active–low) is  
asynchronous and occurs when a low level is applied to the Reset  
input. Information at a D input is transferred to the corresponding Q  
output on the next positive going edge of the Clock input.  
MARKING  
DIAGRAMS  
16  
PDIP–16  
N SUFFIX  
CASE 648  
MC74HC175AN  
AWLYYWW  
16  
16  
1
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
1
16  
SO–16  
D SUFFIX  
CASE 751B  
HC175A  
AWLYWW  
Low Input Current: 1 µA  
1
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
1
16  
HC  
175A  
ALYW  
TSSOP–16  
DT SUFFIX  
CASE 948F  
Chip Complexity 166 FETs or 41.5 Equivalent Gates  
16  
1
LOGIC DIAGRAM  
1
A
= Assembly Location  
9
2
3
CLOCK  
Q0  
Q0  
WL = Wafer Lot  
YY = Year  
WW = Work Week  
7
6
10  
Q1  
Q1  
Q2  
INVERTING  
AND  
NONINVERTING  
OUTPUTS  
4
5
D0  
D1  
DATA  
INPUTS  
PIN ASSIGNMENT  
11  
15  
14  
Q2  
Q3  
Q3  
12  
13  
D2  
D3  
RESET  
1
2
3
4
5
6
7
8
16  
V
CC  
Q0  
Q0  
15 Q3  
14 Q3  
13 D3  
12 D2  
11 Q2  
10 Q2  
1
RESET  
D0  
PIN 16 = V  
CC  
PIN 8 = GND  
D1  
Q1  
FUNCTION TABLE  
Q1  
Inputs  
Reset Clock  
Outputs  
GND  
9
CLOCK  
D
Q
Q
L
H
H
H
X
X
H
L
L
H
L
H
L
H
L
X
No Change  
ORDERING INFORMATION  
Device  
Package  
PDIP–16  
SOIC–16  
SOIC–16  
TSSOP–16  
Shipping  
MC74HC175AN  
2000 / Box  
48 / Rail  
MC74HC175AD  
MC74HC175ADR2  
MC74HC175ADT  
MC74HC175ADTR2  
2500 / Reel  
96 / Rail  
TSSOP–16 2500 / Reel  
Semiconductor Components Industries, LLC, 1999  
1
Publication Order Number:  
March, 2000 – Rev. 2  
MC74HC175A/D  

MC74HC175AN 替代型号

型号 品牌 替代类型 描述 数据表
SN74HC175N TI

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