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MC74HC175ND PDF预览

MC74HC175ND

更新时间: 2024-11-02 13:11:19
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 触发器时钟
页数 文件大小 规格书
7页 203K
描述
HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16

MC74HC175ND 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP16,.3Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.66
系列:HC/UHJESD-30 代码:R-PDIP-T16
JESD-609代码:e0长度:18.86 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
位数:4功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 V传播延迟(tpd):45 ns
认证状态:Not Qualified座面最大高度:4.69 mm
子类别:FF/Latches最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:7.62 mm
最小 fmax:20 MHzBase Number Matches:1

MC74HC175ND 数据手册

 浏览型号MC74HC175ND的Datasheet PDF文件第2页浏览型号MC74HC175ND的Datasheet PDF文件第3页浏览型号MC74HC175ND的Datasheet PDF文件第4页浏览型号MC74HC175ND的Datasheet PDF文件第5页浏览型号MC74HC175ND的Datasheet PDF文件第6页浏览型号MC74HC175ND的Datasheet PDF文件第7页 
SEMICONDUCTOR TECHNICAL DATA  
High–Performance Silicon–Gate CMOS  
J SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
The MC54/74HC175 is identical in pinout to the LS175. The device inputs  
are compatible with standard CMOS outputs; with pullup resistors, they are  
compatible with LSTTL outputs.  
16  
1
This device consists of four D flip–flops with common Reset and Clock  
inputs, and separate D inputs. Reset (active–low) is asynchronous and  
occurs when a low level is applied to the Reset input. Information at a D input  
is transferred to the corresponding Q output on the next positive going edge  
of the Clock input.  
N SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
16  
1
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
D SUFFIX  
SOIC PACKAGE  
CASE 751B–05  
16  
Low Input Current: 1 µA  
1
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
ORDERING INFORMATION  
MC54HCXXXJ  
MC74HCXXXN  
MC74HCXXXD  
Ceramic  
Plastic  
SOIC  
Chip Complexity 166 FETs or 41.5 Equivalent Gates  
LOGIC DIAGRAM  
9
2
3
CLOCK  
Q0  
Q0  
PIN ASSIGNMENT  
7
6
10  
Q1  
Q1  
Q2  
RESET  
1
2
16  
15  
V
CC  
INVERTING  
AND  
NONINVERTING  
OUTPUTS  
4
5
D0  
D1  
Q0  
Q3  
DATA  
INPUTS  
11  
15  
14  
Q0  
D0  
3
4
5
6
7
8
14  
13  
12  
11  
10  
9
Q3  
Q2  
Q3  
Q3  
12  
13  
D2  
D3  
D3  
D1  
D2  
1
RESET  
Q1  
Q2  
Q1  
Q2  
PIN 16 = V  
CC  
PIN 8 = GND  
GND  
CLOCK  
FUNCTION TABLE  
Inputs  
Reset Clock  
Outputs  
D
Q
Q
L
H
H
H
X
X
H
L
L
H
L
H
L
H
L
X
No Change  
10/95  
Motorola, Inc. 1995  
REV 6  

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