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MC74HC175 PDF预览

MC74HC175

更新时间: 2024-11-29 23:05:47
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 触发器时钟
页数 文件大小 规格书
7页 203K
描述
Quad D Flip-Flop with Common Clock and Reset

MC74HC175 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
High–Performance Silicon–Gate CMOS  
J SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
The MC54/74HC175 is identical in pinout to the LS175. The device inputs  
are compatible with standard CMOS outputs; with pullup resistors, they are  
compatible with LSTTL outputs.  
16  
1
This device consists of four D flip–flops with common Reset and Clock  
inputs, and separate D inputs. Reset (active–low) is asynchronous and  
occurs when a low level is applied to the Reset input. Information at a D input  
is transferred to the corresponding Q output on the next positive going edge  
of the Clock input.  
N SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
16  
1
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
D SUFFIX  
SOIC PACKAGE  
CASE 751B–05  
16  
Low Input Current: 1 µA  
1
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
ORDERING INFORMATION  
MC54HCXXXJ  
MC74HCXXXN  
MC74HCXXXD  
Ceramic  
Plastic  
SOIC  
Chip Complexity 166 FETs or 41.5 Equivalent Gates  
LOGIC DIAGRAM  
9
2
3
CLOCK  
Q0  
Q0  
PIN ASSIGNMENT  
7
6
10  
Q1  
Q1  
Q2  
RESET  
1
2
16  
15  
V
CC  
INVERTING  
AND  
NONINVERTING  
OUTPUTS  
4
5
D0  
D1  
Q0  
Q3  
DATA  
INPUTS  
11  
15  
14  
Q0  
D0  
3
4
5
6
7
8
14  
13  
12  
11  
10  
9
Q3  
Q2  
Q3  
Q3  
12  
13  
D2  
D3  
D3  
D1  
D2  
1
RESET  
Q1  
Q2  
Q1  
Q2  
PIN 16 = V  
CC  
PIN 8 = GND  
GND  
CLOCK  
FUNCTION TABLE  
Inputs  
Reset Clock  
Outputs  
D
Q
Q
L
H
H
H
X
X
H
L
L
H
L
H
L
H
L
X
No Change  
10/95  
Motorola, Inc. 1995  
REV 6  

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