是否无铅: | 含铅 | 是否Rohs认证: | 不符合 |
生命周期: | Obsolete | 包装说明: | DIP, DIP14,.3 |
Reach Compliance Code: | unknown | HTS代码: | 8542.39.00.01 |
风险等级: | 5.92 | JESD-30 代码: | R-PDIP-T14 |
JESD-609代码: | e0 | 负载电容(CL): | 50 pF |
逻辑集成电路类型: | NAND GATE | 最大I(ol): | 0.004 A |
端子数量: | 14 | 最高工作温度: | 85 °C |
最低工作温度: | -40 °C | 封装主体材料: | PLASTIC/EPOXY |
封装代码: | DIP | 封装等效代码: | DIP14,.3 |
封装形状: | RECTANGULAR | 封装形式: | IN-LINE |
峰值回流温度(摄氏度): | NOT SPECIFIED | 电源: | 2/6 V |
Prop。Delay @ Nom-Sup: | 24 ns | 施密特触发器: | NO |
子类别: | Gates | 表面贴装: | NO |
技术: | CMOS | 温度等级: | INDUSTRIAL |
端子面层: | Tin/Lead (Sn/Pb) | 端子形式: | THROUGH-HOLE |
端子节距: | 2.54 mm | 端子位置: | DUAL |
处于峰值回流温度下的最长时间: | NOT SPECIFIED | Base Number Matches: | 1 |
型号 | 品牌 | 获取价格 | 描述 | 数据表 |
MC74HC10NS | ROCHESTER |
获取价格 |
AND Gate | |
MC74HC11 | MOTOROLA |
获取价格 |
Dual J-K Flip-Flop with Set and Reset | |
MC74HC112 | ONSEMI |
获取价格 |
Dual J-K Flip-Flop with Set and Reset | |
MC74HC112_13 | ONSEMI |
获取价格 |
Dual J-K Flip-Flop with Set and Reset | |
MC74HC112A | ONSEMI |
获取价格 |
Dual J-K Flip-Flop with Set and Reset High−Performance Silicon−Gate CMOS | |
MC74HC112ADG | ONSEMI |
获取价格 |
Dual J-K Flip-Flop with Set and Reset High−Performance Silicon−Gate CMOS | |
MC74HC112ADR2G | ONSEMI |
获取价格 |
Dual J-K Flip-Flop with Set and Reset High−Performance Silicon−Gate CMOS | |
MC74HC112ADTG | ONSEMI |
获取价格 |
暂无描述 | |
MC74HC112ADTR2G | ONSEMI |
获取价格 |
Dual J-K Flip-Flop with Set and Reset High−Performance Silicon−Gate CMOS | |
MC74HC112AFELG | ONSEMI |
获取价格 |
Dual J-K Flip-Flop with Set and Reset High−Performance Silicon−Gate CMOS |