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MC74HC112DDS PDF预览

MC74HC112DDS

更新时间: 2024-11-18 13:11:19
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 触发器
页数 文件大小 规格书
6页 214K
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MC74HC112DDS 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
High–Performance Silicon–Gate CMOS  
N SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
16  
The MC74HC112 is identical in pinout to the LS112. The device inputs are  
compatible with standard CMOS outputs; with pullup resistors, they are  
compatible with LSTTL outputs.  
1
Each flip–flop is negative–edge clocked and has active–low asynchro-  
nous Set and Reset inputs.  
The HC112 is identical in function to the HC76, but has a different pinout.  
D SUFFIX  
SOIC PACKAGE  
CASE 751B–05  
16  
1
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
DT SUFFIX  
TSSOP PACKAGE  
CASE 948F–01  
16  
Low Input Current: 1 µA  
1
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
ORDERING INFORMATION  
Similar in Function to the LS112 Except When Set and Reset are Low  
Simultaneously  
Chip Complexity: 100 FETs or 25 Equivalent Gates  
MC74HCXXXN  
MC74HCXXXD  
MC74HCXXXDT  
Plastic  
SOIC  
TSSOP  
PIN ASSIGNMENT  
LOGIC DIAGRAM  
CLOCK 1  
1
2
16  
15  
V
CC  
K1  
J1  
RESET 1  
4
SET 1  
3
4
14  
13  
RESET 2  
CLOCK 2  
2
1
5
6
SET 1  
Q1  
K1  
Q1  
Q1  
5
6
12  
11  
K2  
J2  
CLOCK 1  
Q1  
3
J1  
Q2  
7
8
10  
9
SET 2  
Q2  
15  
RESET 1  
GND  
10  
FUNCTION TABLE  
Inputs  
SET 2  
Outputs  
12  
13  
9
K2  
Q2  
Q2  
Set Reset Clock  
J
K
Q
Q
CLOCK 2  
L
H
L
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
X
X
X
X
X
X
L
X
X
X
L
H
L
L
H
11  
14  
7
J2  
L*  
L*  
No Change  
RESET 2  
L
H
L
H
X
X
X
L
H
H
L
H
H
X
X
X
Toggle  
PIN 16 = V  
CC  
PIN 8 = GND  
L
H
No Change  
No Change  
No Change  
* Both outputs will remain low as long as Set and  
Reset are low, but the output states are unpre-  
dictable if Set and Reset go high simultaneously.  
10/95  
REV 6  
Motorola, Inc. 1995  

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