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MC74HC112ND PDF预览

MC74HC112ND

更新时间: 2024-01-03 00:45:22
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 触发器
页数 文件大小 规格书
6页 214K
描述
HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16

MC74HC112ND 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP16,.3Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.71
系列:HC/UHJESD-30 代码:R-PDIP-T16
JESD-609代码:e0长度:18.86 mm
负载电容(CL):50 pF逻辑集成电路类型:J-K FLIP-FLOP
位数:2功能数量:2
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 V传播延迟(tpd):38 ns
认证状态:Not Qualified座面最大高度:4.69 mm
子类别:FF/Latches最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:NEGATIVE EDGE宽度:7.62 mm
最小 fmax:20 MHzBase Number Matches:1

MC74HC112ND 数据手册

 浏览型号MC74HC112ND的Datasheet PDF文件第2页浏览型号MC74HC112ND的Datasheet PDF文件第3页浏览型号MC74HC112ND的Datasheet PDF文件第4页浏览型号MC74HC112ND的Datasheet PDF文件第5页浏览型号MC74HC112ND的Datasheet PDF文件第6页 
SEMICONDUCTOR TECHNICAL DATA  
High–Performance Silicon–Gate CMOS  
N SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
16  
The MC74HC112 is identical in pinout to the LS112. The device inputs are  
compatible with standard CMOS outputs; with pullup resistors, they are  
compatible with LSTTL outputs.  
1
Each flip–flop is negative–edge clocked and has active–low asynchro-  
nous Set and Reset inputs.  
The HC112 is identical in function to the HC76, but has a different pinout.  
D SUFFIX  
SOIC PACKAGE  
CASE 751B–05  
16  
1
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
DT SUFFIX  
TSSOP PACKAGE  
CASE 948F–01  
16  
Low Input Current: 1 µA  
1
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
ORDERING INFORMATION  
Similar in Function to the LS112 Except When Set and Reset are Low  
Simultaneously  
Chip Complexity: 100 FETs or 25 Equivalent Gates  
MC74HCXXXN  
MC74HCXXXD  
MC74HCXXXDT  
Plastic  
SOIC  
TSSOP  
PIN ASSIGNMENT  
LOGIC DIAGRAM  
CLOCK 1  
1
2
16  
15  
V
CC  
K1  
J1  
RESET 1  
4
SET 1  
3
4
14  
13  
RESET 2  
CLOCK 2  
2
1
5
6
SET 1  
Q1  
K1  
Q1  
Q1  
5
6
12  
11  
K2  
J2  
CLOCK 1  
Q1  
3
J1  
Q2  
7
8
10  
9
SET 2  
Q2  
15  
RESET 1  
GND  
10  
FUNCTION TABLE  
Inputs  
SET 2  
Outputs  
12  
13  
9
K2  
Q2  
Q2  
Set Reset Clock  
J
K
Q
Q
CLOCK 2  
L
H
L
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
X
X
X
X
X
X
L
X
X
X
L
H
L
L
H
11  
14  
7
J2  
L*  
L*  
No Change  
RESET 2  
L
H
L
H
X
X
X
L
H
H
L
H
H
X
X
X
Toggle  
PIN 16 = V  
CC  
PIN 8 = GND  
L
H
No Change  
No Change  
No Change  
* Both outputs will remain low as long as Set and  
Reset are low, but the output states are unpre-  
dictable if Set and Reset go high simultaneously.  
10/95  
REV 6  
Motorola, Inc. 1995  

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