Datasheet > MC74HC112

MC74HC112

更新时间： 2024-11-19 01:15:47

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
7页	138K
描述
Dual J-K Flip-Flop with Set and Reset

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中文翻译

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数据手册

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MC74HC112 数据手册

MC74HC112A

Dual J-K Flip-Flop with

Set and Reset

High−Performance Silicon−Gate CMOS

The MC74HC112A is identical in pinout to the LS112. The device

inputs are compatible with standard CMOS outputs; with pullup

resistors, they are compatible with LSTTL outputs.

Each flip−flop is negative−edge clocked and has active−low

asynchronous Set and Reset inputs.

http://onsemi.com

MARKING

DIAGRAMS

The HC112A is identical in function to the HC76, but has a different

pinout.

SOIC−16

D SUFFIX

CASE 751B

HC112AG

AWLYWW

Features

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 mA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

TSSOP−16

DT SUFFIX

CASE 948F

112A

ALYWG

• Similar in Function to the LS112 Except When Set and Reset are

Low Simultaneously

• Chip Complexity: 100 FETs or 25 Equivalent Gates

• These are Pb−Free Devices

L, WL

Y, YY

= Assembly Location

= Wafer Lot

= Year

W, WW = Work Week

= Pb−Free Package

(Note: Microdot may be in either location)

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

Publication Order Number:

May, 2013 − Rev. 8

MC74HC112/D

12 3 4 5 6 7

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MC74HC112_13	ONSEMI	获取价格	Dual J-K Flip-Flop with Set and Reset
MC74HC112A	ONSEMI	获取价格	Dual J-K Flip-Flop with Set and Reset High−Performance Silicon−Gate CMOS
MC74HC112ADG	ONSEMI	获取价格	Dual J-K Flip-Flop with Set and Reset High−Performance Silicon−Gate CMOS
MC74HC112ADR2G	ONSEMI	获取价格	Dual J-K Flip-Flop with Set and Reset High−Performance Silicon−Gate CMOS
MC74HC112ADTG	ONSEMI	获取价格	暂无描述
MC74HC112ADTR2G	ONSEMI	获取价格	Dual J-K Flip-Flop with Set and Reset High−Performance Silicon−Gate CMOS
MC74HC112AFELG	ONSEMI	获取价格	Dual J-K Flip-Flop with Set and Reset High−Performance Silicon−Gate CMOS
MC74HC112ANG	ONSEMI	获取价格	Dual J-K Flip-Flop with Set and Reset High−Performance Silicon−Gate CMOS
MC74HC112D	MOTOROLA	获取价格	Dual J-K Flip-Flop with Set and Reset
MC74HC112DD	MOTOROLA	获取价格	J-K Flip-Flop, 2-Func, Negative Edge Triggered, CMOS, PDSO16