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MC14043B

更新时间： 2024-11-11 22:58:11
品牌 Logo 应用领域
安森美 - ONSEMI 锁存器
页数 文件大小 规格书
8页 196K
描述
CMOS MSI(Quad R-S Latches)

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MC14043B 数据手册

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Quad R–S Latches  
The MC14043B and MC14044B quad R–S latches are constructed  
with MOS P–channel and N–channel enhancement mode devices in a  
single monolithic structure. Each latch has an independent Q output  
and set and reset inputs. The Q outputs are gated through three–state  
buffers having a common enable input. The outputs are enabled with a  
logical “1” or high on the enable input; a logical “0” or low  
disconnects the latch from the Q outputs, resulting in an open circuit at  
the Q outputs.  
http://onsemi.com  
MARKING  
DIAGRAMS  
16  
PDIP–16  
P SUFFIX  
CASE 648  
MC140XXBCP  
AWLYYWW  
• Double Diode Input Protection  
• Three–State Outputs with Common Enable  
1
• Outputs Capable of Driving Two Low–power TTL Loads or One  
Low–Power Schottky TTL Load Over the Rated Temperature Range  
• Supply Voltage Range = 3.0 Vdc to 18 Vdc  
16  
SOIC–16  
D SUFFIX  
CASE 751B  
140XXB  
AWLYWW  
1
16  
MAXIMUM RATINGS (Voltages Referenced to V ) (Note 2.)  
SS  
SOEIAJ–16  
F SUFFIX  
CASE 966  
MC140XXB  
AWLYWW  
Symbol  
Parameter  
Value  
Unit  
V
V
DD  
DC Supply Voltage Range  
–0.5 to +18.0  
1
V , V  
Input or Output Voltage Range  
(DC or Transient)  
–0.5 to V + 0.5  
V
in out  
DD  
XX  
A
= Specific Device Code  
= Assembly Location  
I , I  
in out  
Input or Output Current  
(DC or Transient) per Pin  
±10  
mA  
WL or L = Wafer Lot  
YY or Y = Year  
WW or W = Work Week  
P
D
Power Dissipation,  
per Package (Note 3.)  
500  
mW  
T
Ambient Temperature Range  
Storage Temperature Range  
–55 to +125  
–65 to +150  
260  
°C  
°C  
°C  
A
ORDERING INFORMATION  
T
stg  
Device  
Package  
PDIP–16  
SOIC–16  
Shipping  
T
Lead Temperature  
L
(8–Second Soldering)  
MC14043BCP  
MC14043BD  
2000/Box  
2400/Box  
2. Maximum Ratings are those values beyond which damage to the device  
may occur.  
3. Temperature Derating:  
MC14043BDR2  
SOIC–16 2500/Tape & Reel  
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
MC14043BF  
MC14043BFEL  
MC14044BCP  
MC14044BD  
SOEIAJ–16  
SOEIAJ–16  
PDIP–16  
See Note 1.  
See Note 1.  
2000/Box  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
high–impedancecircuit. For proper operation, V and V should be constrained  
in  
out  
to the range V  
(V or V  
)
V
DD  
.
SS  
in  
out  
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,  
either V or V ). Unused outputs must be left open.  
SOIC–16  
2400/Box  
SS  
DD  
MC14044BDR2  
SOIC–16 2500/Tape & Reel  
1. For ordering information on the EIAJ version of  
the SOIC packages, please contact your local  
ON Semiconductor representative.  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
March, 2000 – Rev. 3  
MC14043B/D  
12345678

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