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MC14043B_05

更新时间： 2024-09-26 04:59:31
品牌 Logo 应用领域
安森美 - ONSEMI 锁存器
页数 文件大小 规格书
8页 104K
描述
CMOS MSI Quad R−S Latches

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MC14043B_05 数据手册

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MC14043B, MC14044B  
CMOS MSI  
Quad R−S Latches  
The MC14043B and MC14044B quad R−S latches are constructed  
with MOS P−Channel and N−Channel enhancement mode devices in a  
single monolithic structure. Each latch has an independent Q output  
and set and reset inputs. The Q outputs are gated through three−state  
buffers having a common enable input. The outputs are enabled with a  
logical “1” or high on the enable input; a logical “0” or low  
disconnects the latch from the Q outputs, resulting in an open circuit at  
the Q outputs.  
http://onsemi.com  
MARKING  
DIAGRAMS  
16  
1
PDIP−16  
P SUFFIX  
CASE 648  
MC140xxBCP  
AWLYYWWG  
Features  
• Double Diode Input Protection  
• Three−State Outputs with Common Enable  
• Outputs Capable of Driving Two Low−power TTL Loads or One  
Low−Power Schottky TTL Load Over the Rated Temperature Range  
• Supply Voltage Range = 3.0 Vdc to 18 Vdc  
• Pb−Free Packages are Available*  
16  
SOIC−16  
D SUFFIX  
CASE 751B  
140xxBG  
AWLYWW  
1
MAXIMUM RATINGS (Voltages Referenced to V  
)
SS  
Symbol  
Parameter  
Value  
Unit  
V
16  
V
DC Supply Voltage Range  
−0.5 to +18.0  
SOEIAJ−16  
F SUFFIX  
CASE 966  
DD  
MC140xxB  
ALYWG  
V , V  
in out  
Input or Output Voltage Range  
(DC or Transient)  
−0.5 to V + 0.5  
V
DD  
1
I , I  
Input or Output Current  
(DC or Transient) per Pin  
± 10  
mA  
in out  
xx  
A
WL, L  
YY, Y  
= Specific Device Code  
= Assembly Location  
= Wafer Lot  
P
T
Power Dissipation, per Package  
(Note 1)  
500  
mW  
D
= Year  
Ambient Temperature Range  
Storage Temperature Range  
−55 to +125  
−65 to +150  
260  
°C  
°C  
°C  
WW, W = Work Week  
G
A
= Pb−Free Indicator  
T
stg  
T
Lead Temperature  
(8−Second Soldering)  
L
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 5 of this data sheet.  
Maximum ratings are those values beyond which device damage can occur.  
Maximum ratings applied to the device are individual stress limit values (not  
normal operating conditions) and are not valid simultaneously. If these limits are  
exceeded, device functional operation is not implied, damage may occur and  
reliability may be affected.  
1. Temperature Derating:  
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
high−impedance circuit. For proper operation, V and V should be constrained  
in  
out  
to the range V v (V or V ) v V  
.
DD  
SS  
in  
out  
Unused inputs must always be tied to an appropriate logic voltage level  
(e.g., either V or V ). Unused outputs must be left open.  
SS  
DD  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
August, 2005 − Rev. 6  
MC14043B/D  
 
12345678

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