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MC14043BDR2G PDF预览

MC14043BDR2G

更新时间: 2024-02-25 15:10:23
品牌 Logo 应用领域
安森美 - ONSEMI 触发器锁存器逻辑集成电路光电二极管PC
页数 文件大小 规格书
8页 104K
描述
CMOS MSI Quad R−S Latches

MC14043BDR2G 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP16,.25针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:0.85
Samacsys Confidence:3Samacsys Status:Released
Samacsys PartID:1183324Samacsys Pin Count:16
Samacsys Part Category:Integrated CircuitSamacsys Package Category:Small Outline Packages
Samacsys Footprint Name:MC14043BDR2GSamacsys Released Date:2019-05-19 15:04:59
Is Samacsys:N系列:4000/14000/40000
JESD-30 代码:R-PDSO-G16JESD-609代码:e3
长度:9.9 mm负载电容(CL):50 pF
逻辑集成电路类型:R-S LATCH湿度敏感等级:1
位数:4功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:5/15 VProp。Delay @ Nom-Sup:350 ns
传播延迟(tpd):350 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:FF/Latches
最大供电电压 (Vsup):18 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40触发器类型:HIGH LEVEL
宽度:3.9 mmBase Number Matches:1

MC14043BDR2G 数据手册

 浏览型号MC14043BDR2G的Datasheet PDF文件第2页浏览型号MC14043BDR2G的Datasheet PDF文件第3页浏览型号MC14043BDR2G的Datasheet PDF文件第4页浏览型号MC14043BDR2G的Datasheet PDF文件第5页浏览型号MC14043BDR2G的Datasheet PDF文件第6页浏览型号MC14043BDR2G的Datasheet PDF文件第7页 
MC14043B, MC14044B  
CMOS MSI  
Quad R−S Latches  
The MC14043B and MC14044B quad R−S latches are constructed  
with MOS P−Channel and N−Channel enhancement mode devices in a  
single monolithic structure. Each latch has an independent Q output  
and set and reset inputs. The Q outputs are gated through three−state  
buffers having a common enable input. The outputs are enabled with a  
logical “1” or high on the enable input; a logical “0” or low  
disconnects the latch from the Q outputs, resulting in an open circuit at  
the Q outputs.  
http://onsemi.com  
MARKING  
DIAGRAMS  
16  
1
PDIP−16  
P SUFFIX  
CASE 648  
MC140xxBCP  
AWLYYWWG  
Features  
Double Diode Input Protection  
Three−State Outputs with Common Enable  
Outputs Capable of Driving Two Low−power TTL Loads or One  
Low−Power Schottky TTL Load Over the Rated Temperature Range  
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
Pb−Free Packages are Available*  
16  
SOIC−16  
D SUFFIX  
CASE 751B  
140xxBG  
AWLYWW  
1
MAXIMUM RATINGS (Voltages Referenced to V  
)
SS  
Symbol  
Parameter  
Value  
Unit  
V
16  
V
DC Supply Voltage Range  
0.5 to +18.0  
SOEIAJ−16  
F SUFFIX  
CASE 966  
DD  
MC140xxB  
ALYWG  
V , V  
in out  
Input or Output Voltage Range  
(DC or Transient)  
0.5 to V + 0.5  
V
DD  
1
I , I  
Input or Output Current  
(DC or Transient) per Pin  
± 10  
mA  
in out  
xx  
A
WL, L  
YY, Y  
= Specific Device Code  
= Assembly Location  
= Wafer Lot  
P
T
Power Dissipation, per Package  
(Note 1)  
500  
mW  
D
= Year  
Ambient Temperature Range  
Storage Temperature Range  
55 to +125  
65 to +150  
260  
°C  
°C  
°C  
WW, W = Work Week  
G
A
= Pb−Free Indicator  
T
stg  
T
Lead Temperature  
(8−Second Soldering)  
L
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 5 of this data sheet.  
Maximum ratings are those values beyond which device damage can occur.  
Maximum ratings applied to the device are individual stress limit values (not  
normal operating conditions) and are not valid simultaneously. If these limits are  
exceeded, device functional operation is not implied, damage may occur and  
reliability may be affected.  
1. Temperature Derating:  
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
high−impedance circuit. For proper operation, V and V should be constrained  
in  
out  
to the range V v (V or V ) v V  
.
DD  
SS  
in  
out  
Unused inputs must always be tied to an appropriate logic voltage level  
(e.g., either V or V ). Unused outputs must be left open.  
SS  
DD  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
August, 2005 − Rev. 6  
MC14043B/D  
 

MC14043BDR2G 替代型号

型号 品牌 替代类型 描述 数据表
MC14043BDG ONSEMI

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CMOS MSI Quad R−S Latches
CD4043BM TI

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CMOS QUAD 3-STATE R/S LATCHES
CD4043BD TI

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CMOS QUAD 3-STATE R/S LATCHES

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