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MC14043BFL1 PDF预览

MC14043BFL1

更新时间： 2024-09-26 19:45:11
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
10页 128K
描述
R-S Latch, 4000/14000/40000 Series, 1-Func, High Level Triggered, 4-Bit, True Output, CMOS, PDSO16, EIAJ, PLASTIC, SOIC-16

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MC14043BFL1 技术参数

生命周期：Contact Manufacturer包装说明：SOP,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.62系列：4000/14000/40000
JESD-30 代码：R-PDSO-G16长度：10.2 mm
逻辑集成电路类型：R-S LATCH位数：4
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
传播延迟（tpd）：350 ns座面最大高度：2.05 mm
最大供电电压 (Vsup)：18 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL触发器类型：HIGH LEVEL
宽度：5.275 mmBase Number Matches：1

MC14043BFL1 数据手册

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MC14043B, MC14044B  
CMOS MSI  
Quad R–S Latches  
The MC14043B and MC14044B quad R–S latches are constructed  
with MOS P–channel and N–channel enhancement mode devices in a  
single monolithic structure. Each latch has an independent Q output  
and set and reset inputs. The Q outputs are gated through three–state  
buffers having a common enable input. The outputs are enabled with a  
logical “1” or high on the enable input; a logical “0” or low  
disconnects the latch from the Q outputs, resulting in an open circuit at  
the Q outputs.  
http://onsemi.com  
MARKING  
DIAGRAMS  
16  
PDIP–16  
P SUFFIX  
CASE 648  
MC140xxBCP  
AWLYYWW  
• Double Diode Input Protection  
• Three–State Outputs with Common Enable  
1
• Outputs Capable of Driving Two Low–power TTL Loads or One  
Low–Power Schottky TTL Load Over the Rated Temperature Range  
• Supply Voltage Range = 3.0 Vdc to 18 Vdc  
16  
SOIC–16  
D SUFFIX  
CASE 751B  
140xxB  
AWLYWW  
1
16  
MAXIMUM RATINGS (Voltages Referenced to V ) (Note 2.)  
SS  
SOEIAJ–16  
F SUFFIX  
CASE 966  
MC140xxB  
ALYW  
Symbol  
Parameter  
Value  
Unit  
V
V
DD  
DC Supply Voltage Range  
–0.5 to +18.0  
1
V , V  
Input or Output Voltage Range  
(DC or Transient)  
–0.5 to V + 0.5  
V
in out  
DD  
xx  
A
WL, L  
YY, Y  
= Specific Device Code  
= Assembly Location  
= Wafer Lot  
I , I  
in out  
Input or Output Current  
(DC or Transient) per Pin  
±10  
mA  
= Year  
P
D
Power Dissipation,  
per Package (Note 3.)  
500  
mW  
WW, W = Work Week  
T
Ambient Temperature Range  
Storage Temperature Range  
–55 to +125  
–65 to +150  
260  
°C  
°C  
°C  
A
ORDERING INFORMATION  
T
stg  
Device  
Package  
PDIP–16  
SOIC–16  
Shipping  
T
Lead Temperature  
L
(8–Second Soldering)  
MC14043BCP  
MC14043BD  
2000/Box  
2400/Box  
2. Maximum Ratings are those values beyond which damage to the device  
may occur.  
3. Temperature Derating:  
MC14043BDR2  
SOIC–16 2500/Tape & Reel  
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C  
MC14043BF  
MC14043BFEL  
MC14044BCP  
MC14044BD  
SOEIAJ–16  
SOEIAJ–16  
PDIP–16  
See Note 1.  
See Note 1.  
2000/Box  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
high–impedance circuit. For proper operation, V and V should be constrained  
in  
out  
to the range V v (V or V ) v V  
.
SS  
in  
out  
DD  
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,  
SOIC–16  
2400/Box  
either V or V ). Unused outputs must be left open.  
SS  
DD  
MC14044BDR2  
SOIC–16 2500/Tape & Reel  
1. For ordering information on the EIAJ version of  
the SOIC packages, please contact your local  
ON Semiconductor representative.  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
August, 2000 – Rev. 4  
MC14043B/D  
1234567...10

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