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MC14006BCPD

更新时间： 2024-01-03 23:44:34
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 移位寄存器
页数 文件大小 规格书
6页 109K
描述
4000/14000/40000 SERIES, 5-BIT RIGHT SERIAL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP14, 646-06

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中文翻译

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MC14006BCPD 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：DIP, DIP14,.3Reach Compliance Code：unknown
风险等级：5.92JESD-30 代码：R-XDIP-T14
JESD-609代码：e0位数：5
功能数量：1端子数量：14
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：CERAMIC封装代码：DIP
封装等效代码：DIP14,.3封装形状：RECTANGULAR
封装形式：IN-LINE电源：5/15 V
认证状态：Not Qualified筛选级别：MIL-STD-883 Class B (Modified)
子类别：Shift Registers表面贴装：NO
技术：CMOS温度等级：MILITARY
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
Base Number Matches：1

MC14006BCPD 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
L SUFFIX  
CERAMIC  
CASE 632  
The MC14006B shift register is comprised of four separate shift register  
sections sharing a common clock: two sections have four stages, and two  
sections have five stages with an output tap on both the fourth and fifth  
stages. This makes it possible to obtain a shift register of 4, 5, 8, 9, 10, 12,  
13, 14, 16, 17, or 18 bits by appropriate selection of inputs and outputs. This  
part is particularly useful in serial shift registers and time delay circuits.  
P SUFFIX  
PLASTIC  
CASE 646  
•
•
•
•
•
Output Transitions Occur on the Falling Edge of the Clock Pulse  
Fully Static Operation  
Can be Cascaded to Provide Longer Shift Register Lengths  
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
Capable of Driving Two Low–power TTL Loads or One Low–power  
Schottky TTL Load Over the Rated Temperature Range  
Pin–for–Pin Replacement for CD4006B  
D SUFFIX  
SOIC  
CASE 751A  
•
ORDERING INFORMATION  
MAXIMUM RATINGS* (Voltages Referenced to V  
)
SS  
MC14XXXBCP  
MC14XXXBCL  
MC14XXXBD  
Plastic  
Ceramic  
SOIC  
Symbol  
Parameter  
DC Supply Voltage  
Value  
Unit  
V
V
– 0.5 to + 18.0  
DD  
V , V  
T
A
= – 55° to 125°C for all packages.  
Input or Output Voltage (DC or Transient)  
– 0.5 to V  
DD  
+ 0.5  
V
in out  
l , l  
in out  
Input or Output Current (DC or Transient),  
per Pin  
± 10  
mA  
P
D
Power Dissipation, per Package†  
Storage Temperature  
500  
mW  
C
TRUTH TABLE  
(Single Stage)  
D
C
Q
n+1  
n
T
stg  
– 65 to + 150  
260  
0
1
x
0
1
T
L
Lead Temperature (8–Second Soldering)  
C
Q
n
* Maximum Ratings are those values beyond which damage to the device may occur.  
†Temperature Derating:  
X = Don’t Care  
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C  
BLOCK DIAGRAM  
1
13  
4
11  
12  
5
10  
6
8
9
D
Q4  
D
Q8  
Q9  
D
Q13  
D
P14  
Q17  
Q18  
P1  
P5  
P10  
V
V
= PIN 14  
= PIN 7  
D
D
D
D
D
D
DD  
SS  
4
4
1
4
4
1
STAGES  
C
STAGES  
C
STAGE  
C
STAGES  
C
STAGES  
C
STAGE  
C
NC = PIN 2  
CLOCK 3  
LOGIC DIAGRAM  
(ONE REGISTER STAGE)  
C
C
C
#
*
DATA  
(C)  
D + 1  
* Transmission Gate  
#Inverter used only on the first stage of  
each four–stage element.  
C
1
Input to output is  
IN  
OUT  
(A) A bidirectional low impedance when control input 1 is “low” and control input 2 is “high”.  
(B) An open circuit when control input 1 is “high” and control input 2 is “low”.  
2
(C)  
REV 3  
1/94  
Motorola, Inc. 1995  
123456

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