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MC14007UBCPS PDF预览

MC14007UBCPS

更新时间: 2024-01-06 09:28:24
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA /
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MC14007UBCPS 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
L SUFFIX  
CERAMIC  
CASE 632  
The MC14007UB multi–purpose device consists of three N–channel and  
three P–channel enhancement mode devices packaged to provide access to  
each device. These versatile parts are useful in inverter circuits, pulse–  
shapers, linear amplifiers, high input impedance amplifiers, threshold  
detectors, transmission gating, and functional gating.  
P SUFFIX  
PLASTIC  
CASE 646  
Diode Protection on All Inputs  
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
Capable of Driving Two Low–power TTL Loads or One Low–power  
Schottky TTL Load Over the Rated Temperature Range  
Pin–for–Pin Replacement for CD4007A or CD4007UB  
This device has 2 outputs without ESD Protection. Anti–static  
precautions must be taken.  
D SUFFIX  
SOIC  
CASE 751A  
ORDERING INFORMATION  
MC14XXXUBCP  
MC14XXXUBCL  
MC14XXXUBD  
Plastic  
Ceramic  
SOIC  
MAXIMUM RATINGS* (Voltages Referenced to V  
)
SS  
Symbol  
Parameter  
DC Supply Voltage  
Value  
Unit  
V
T
A
= – 55° to 125°C for all packages.  
V
DD  
– 0.5 to + 18.0  
V , V  
in out  
Input or Output Voltage (DC or Transient)  
– 0.5 to V  
DD  
+ 0.5  
V
l , l  
in out  
Input or Output Current (DC or Transient),  
per Pin  
± 10  
mA  
PIN ASSIGNMENT  
D–P  
S–P  
1
2
3
4
14  
13  
12  
11  
V
B
B
B
B
DD  
D–P  
P
Power Dissipation, per Package†  
Storage Temperature  
500  
mW  
C
D
A
T
stg  
– 65 to + 150  
260  
GATE  
S–N  
OUT  
C
T
Lead Temperature (8–Second Soldering)  
C
L
S–P  
C
* Maximum Ratings are those values beyond which damage to the device may occur.  
Temperature Derating:  
D–N  
5
6
10  
9
GATE  
C
B
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C  
GATE  
S–N  
C
A
V
7
8
D–N  
A
SS  
A
A
D = DRAIN  
S = SOURCE  
12  
1
9
B
B
C
2
4
C
SCHEMATIC  
3
5
14 13  
2
1
11  
INPUT  
V
DD  
14  
11  
6
12  
13  
8
INPUT OUTPUT CONDITION  
INPUT  
6
10  
1
0
A = C, B = OPEN  
A = B, C = OPEN  
7
8
3
4
5
10  
9
7
V
SS  
Substrates of P–channel devices internally  
V
V
= PIN 14  
= PIN 7  
DD  
SS  
connected to V ; substrates of N–channel  
DD  
devices internally connected to V  
.
SS  
Figure 1. Typical Application: 2–Input Analog Multiplexer  
REV 3  
1/94  
Motorola, Inc. 1995  

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