MC14008B
4−Bit Full Adder
The MC14008B 4−bit full adder is constructed with MOS
P−Channel and N−Channel enhancement mode devices in a single
monolithic structure. This device consists of four full adders with fast
internal look−ahead carry output. It is useful in binary addition and
other arithmetic applications. The fast parallel carry output bit allows
high−speed operation when used with other adders in a system.
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Features
MARKING
DIAGRAMS
• Look−Ahead Carry Output
• Diode Protection on All Inputs
• All Outputs Buffered
16
1
PDIP−16
P SUFFIX
CASE 648
MC14008BCP
AWLYYWWG
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low−Power TTL Loads or One
Low−Power Schottky TTL Load Over the Rated Temperature Range
• Pin−for−Pin Replacement for CD4008B
• Pb−Free Packages are Available*
16
SOIC−16
D SUFFIX
CASE 751B
14008BG
AWLYWW
MAXIMUM RATINGS (Voltages Referenced to V
)
SS
Symbol
Parameter
Value
−0.5 to +18.0
Unit
V
1
V
DC Supply Voltage Range
DD
V , V
in out
Input or Output Voltage Range
(DC or Transient)
−0.5 to V + 0.5
V
DD
A
WL, L
YY, Y
= Assembly Location
= Wafer Lot
= Year
I , I
in out
Input or Output Current
(DC or Transient) per Pin
10
mA
WW, W = Work Week
P
Power Dissipation, per Package
(Note 1)
500
mW
G
= Pb−Free Indicator
D
T
Ambient Temperature Range
Storage Temperature Range
−55 to +125
−65 to +150
260
°C
°C
°C
A
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
T
stg
T
Lead Temperature
(8−Second Soldering)
L
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V and V should be constrained
in
out
to the range V v (V or V ) v V
.
DD
SS
in
out
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V or V ). Unused outputs must be left open.
SS
DD
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
August, 2005 − Rev. 6
MC14008B/D