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MC14007UBCP

更新时间: 2024-02-13 18:40:14
品牌 Logo 应用领域
安森美 - ONSEMI 逻辑集成电路光电二极管
页数 文件大小 规格书
8页 243K
描述
Dual Complementary Pair Plus Inverter

MC14007UBCP 数据手册

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The MC14007UB multi–purpose device consists of three  
N–channel and three P–channel enhancement mode devices packaged  
to provide access to each device. These versatile parts are useful in  
inverter circuits, pulse–shapers, linear amplifiers, high input  
impedance amplifiers, threshold detectors, transmission gating, and  
functional gating.  
http://onsemi.com  
MARKING  
DIAGRAMS  
14  
Diode Protection on All Inputs  
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
PDIP–14  
P SUFFIX  
CASE 646  
MC14007UBCP  
AWLYYWW  
Capable of Driving Two Low–power TTL Loads or One Low–power  
Schottky TTL Load Over the Rated Temperature Range  
Pin–for–Pin Replacement for CD4007A or CD4007UB  
This device has 2 outputs without ESD Protection. Anti–static  
precautions must be taken.  
1
14  
SOIC–14  
D SUFFIX  
CASE 751A  
14007U  
AWLYWW  
1
14  
MAXIMUM RATINGS (Voltages Referenced to V ) (Note 2.)  
SS  
TSSOP–14  
DT SUFFIX  
CASE 948G  
14  
007U  
ALYW  
Symbol  
Parameter  
Value  
Unit  
V
V
DD  
DC Supply Voltage Range  
0.5 to +18.0  
V , V  
in out  
Input or Output Voltage Range  
(DC or Transient)  
0.5 to V + 0.5  
V
DD  
1
14  
1
I , I  
Input or Output Current  
(DC or Transient) per Pin  
±10  
mA  
in out  
SOEIAJ–14  
F SUFFIX  
CASE 965  
MC14007U  
AWLYWW  
P
D
Power Dissipation,  
per Package (Note 3.)  
500  
mW  
T
Ambient Temperature Range  
Storage Temperature Range  
55 to +125  
65 to +150  
260  
°C  
°C  
°C  
A
A
= Assembly Location  
WL or L = Wafer Lot  
YY or Y = Year  
WW or W = Work Week  
T
stg  
T
Lead Temperature  
(8–Second Soldering)  
L
2. Maximum Ratings are those values beyond which damage to the device  
may occur.  
3. Temperature Derating:  
ORDERING INFORMATION  
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
Device  
Package  
PDIP–14  
SOIC–14  
Shipping  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
MC14007UBCP  
MC14007UBD  
MC14007UBDR2  
MC14007UBDT  
MC14007UBF  
2000/Box  
55/Rail  
high–impedancecircuit. For proper operation, V and V should be constrained  
in  
out  
SOIC–14 2500/Tape & Reel  
to the range V  
(V or V  
)
V
DD  
.
SS  
in  
out  
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,  
either V or V ). Unused outputs must be left open.  
96/Rail  
TSSOP–14  
SOEIAJ–14  
SS  
DD  
See Note 1.  
See Note 1.  
MC14007UBFEL SOEIAJ–14  
1. For ordering information on the EIAJ version of  
the SOIC packages, please contact your local  
ON Semiconductor representative.  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
March, 2000 – Rev. 3  
MC14007UB/D  

MC14007UBCP 替代型号

型号 品牌 替代类型 描述 数据表
MC14007UBCPG ONSEMI

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