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MC10EP016_06 PDF预览

MC10EP016_06

更新时间: 2024-11-30 04:59:39
品牌 Logo 应用领域
安森美 - ONSEMI 计数器
页数 文件大小 规格书
14页 200K
描述
3.3V / 5V ECL 8−Bit Synchronous Binary Up Counter

MC10EP016_06 数据手册

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MC10EP016, MC100EP016  
3.3V / 5VꢀECL 8−Bit  
Synchronous Binary  
Up Counter  
The MC10/100EP016 is a highspeed synchronous, presettable,  
cascadeable 8bit binary counter. Architecture and operation are the  
same as the MC10E016 in the ECLinPSfamily.  
http://onsemi.com  
MARKING  
The counter features internal feedback to TC gated by the TCLD  
(Terminal Count Load) pin. When TCLD is LOW (or left open, in  
which case it is pulled LOW by the internal pulldowns), the TC  
feedback is disabled, and counting proceeds continuously, with TC  
going LOW to indicate an allone state. When TCLD is HIGH, the TC  
feedback causes the counter to automatically reload upon TC = LOW,  
thus functioning as a programmable counter. The Qn outputs do not  
need to be terminated for the count function to operate properly. To  
minimize noise and power, unused Q outputs should be left  
unterminated.  
DIAGRAM*  
MCxxx  
EP016  
AWLYYWWG  
LQFP32  
FA SUFFIX  
CASE 873A  
COUT and COUT provide differential outputs from a single,  
noncascaded counter or divider application. COUT and COUT  
should not be used in cascade configuration. Only TC should be used  
for a counter or divider cascade chain output.  
A differential clock input has also been added to improve  
performance.  
xxx  
A
WL  
YY  
WW  
G
= 10 or 100  
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= PbFree Package  
The 100 Series contains temperature compensation.  
*For additional marking information, refer to  
Application Note AND8002/D.  
500 ps Typical Propagation Delay  
PECL Mode Operating Range: V = 3.0 V to 5.5 V  
CC  
with V = 0 V  
EE  
NECL Mode Operating Range: V = 0 V  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 12 of this data sheet.  
CC  
with V = 3.0 V to 5.5 V  
EE  
Open Input Default State  
Safety Clamp on Inputs  
Internal TC Feedback (Gated)  
Addition of COUT and COUT  
8Bit  
Differential Clock Input  
V Output  
BB  
Fully Synchronous Counting and TC Generation  
Asynchronous Master Reset  
PbFree Packages are Available*  
*For additional information on our PbFree strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
January, 2006 Rev. 11  
MC10EP016/D  

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