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MC10EP016FAR2 PDF预览

MC10EP016FAR2

更新时间: 2024-11-05 20:14:35
品牌 Logo 应用领域
樱桃 - CHERRY 逻辑集成电路
页数 文件大小 规格书
12页 116K
描述
Binary Counter, PQFP32, PLASTIC, TQFP-32

MC10EP016FAR2 技术参数

生命周期:Obsolete包装说明:PLASTIC, TQFP-32
Reach Compliance Code:unknown风险等级:5.67
JESD-30 代码:S-PQFP-G32逻辑集成电路类型:BINARY COUNTER
端子数量:32封装主体材料:PLASTIC/EPOXY
封装形状:SQUARE封装形式:FLATPACK
认证状态:Not Qualified表面贴装:YES
端子形式:GULL WING端子位置:QUAD
Base Number Matches:1

MC10EP016FAR2 数据手册

 浏览型号MC10EP016FAR2的Datasheet PDF文件第2页浏览型号MC10EP016FAR2的Datasheet PDF文件第3页浏览型号MC10EP016FAR2的Datasheet PDF文件第4页浏览型号MC10EP016FAR2的Datasheet PDF文件第5页浏览型号MC10EP016FAR2的Datasheet PDF文件第6页浏览型号MC10EP016FAR2的Datasheet PDF文件第7页 
MC10EP016, MC100EP016  
3.3V / 5VĄECL 8-Bit  
Synchronous Binary  
Up Counter  
The MC10/100EP016 is a high–speed synchronous, presettable,  
cascadeable 8–bit binary counter. Architecture and operation are the  
same as the MC10E016 in the ECLinPS family.  
http://onsemi.com  
MARKING  
The counter features internal feedback to TC gated by the TCLD  
(Terminal Count Load) pin. When TCLD is LOW (or left open, in  
which case it is pulled LOW by the internal pulldowns), the TC  
feedback is disabled, and counting proceeds continuously, with TC  
going LOW to indicate an all–one state. When TCLD is HIGH, the TC  
feedback causes the counter to automatically reload upon TC = LOW,  
thus functioning as a programmable counter. The Qn outputs do not  
need to be terminated for the count function to operate properly. To  
minimize noise and power, unused Q outputs should be left  
unterminated.  
COUT and COUT have been added to allow cascading to be done  
without adding external components. COUT and COUT should only  
be connected to cascaded MC10/100EP016 inputs such as CE or PE.  
Only TC should be used for a counter chain count output pin.  
A differential clock input has also been added to improve  
performance.  
DIAGRAM*  
TQFP–32  
FA SUFFIX  
CASE 873A  
MCxxx  
EP016  
AWLYYWW  
32  
1
xxx = 10 OR 100  
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
WW = Work Week  
The 100 Series contains temperature compensation.  
*For additional information, see Application Note  
AND8002/D  
500 ps Typical Propagation Delay  
PECL Mode Operating Range: V = 3.0 V to 5.5 V  
CC  
with V = 0 V  
EE  
NECL Mode Operating Range: V = 0 V  
CC  
with V = –3.0 V to –5.5 V  
EE  
ORDERING INFORMATION  
Open Input Default State  
Safety Clamp on Inputs  
Internal TC Feedback (Gated)  
Addition of COUT and COUT  
8–Bit  
Device  
Package  
Shipping  
MC10EP016FA  
TQFP–32 250 Units/Tray  
TQFP–32 2000 Tape & Reel  
TQFP–32 250 Units/Tray  
MC10EP016FAR2  
MC100EP016FA  
MC100EP016FAR2 TQFP–32 2000 Tape & Reel  
Differential Clock Input  
V Output  
BB  
Fully Synchronous Counting and TC Generation  
Asynchronous Master Reset  
Semiconductor Components Industries, LLC, 2001  
1
Publication Order Number:  
July, 2001 – Rev. 7  
MC10EP016/D  

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