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MC10EP05DR2 PDF预览

MC10EP05DR2

更新时间: 2024-11-05 22:18:03
品牌 Logo 应用领域
安森美 - ONSEMI 栅极触发器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 89K
描述
2-Input Differential AND/NAND

MC10EP05DR2 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOIC-8
针数:8Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:7.57
Is Samacsys:N其他特性:NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V
系列:10EJESD-30 代码:R-PDSO-G8
JESD-609代码:e0长度:4.9 mm
逻辑集成电路类型:AND/NAND GATE湿度敏感等级:1
功能数量:1输入次数:2
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):240
电源:-5.2 V最大电源电流(ICC):29 mA
Prop。Delay @ Nom-Sup:0.32 ns传播延迟(tpd):0.27 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:1.75 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:ECL温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3.9 mm
Base Number Matches:1

MC10EP05DR2 数据手册

 浏览型号MC10EP05DR2的Datasheet PDF文件第2页浏览型号MC10EP05DR2的Datasheet PDF文件第3页浏览型号MC10EP05DR2的Datasheet PDF文件第4页浏览型号MC10EP05DR2的Datasheet PDF文件第5页浏览型号MC10EP05DR2的Datasheet PDF文件第6页浏览型号MC10EP05DR2的Datasheet PDF文件第7页 
The MC10EP05 is a 2–input differential AND/NAND gate. The  
device is functionally equivalent to the EL05 and LVEL05 devices.  
With AC performance much faster than the LVEL05 device, the EP05  
is ideal for applications requiring the fastest AC performance  
available.  
http://onsemi.com  
170ps Typical Propagation Delay  
High Bandwidth to 3 Ghz Typical  
ECL mode: 0V V  
PECL mode: 3.0V to 5.5V V  
CC  
with V = –3.0V to –5.5V  
CC  
EE  
8
with V = 0V  
EE  
Internal Input Resistors: Pulldown on D, Pulldown and Pullup on D  
1
Q Output will default LOW with inputs open or at V  
ESD Protection: >4KV HBM, >200V MM  
New Differential Input Common Mode Range  
EE  
SO–8  
D SUFFIX  
CASE 751  
Moisture Sensitivity Level 1, Indefinite Time Out of Drypack.  
For Additional Information, See Application Note AND8003/D  
Flammability Rating: UL–94 code V–0 @ 1/8”,  
Oxygen Index 28 to 34  
MARKING DIAGRAM  
8
1
A = Assembly Location  
HEP05  
ALYW  
L = Wafer Lot  
Y = Year  
Transistor Count = 137 devices  
W = Work Week  
*For additional information, see Application Note  
AND8002/D  
D
1
2
8
7
V
CC  
0
PIN DESCRIPTION  
PIN  
D0, D1, D0, D1  
Q, Q  
FUNCTION  
D
0
Q
Q
ECL Data Inputs  
ECL Data Outputs  
D
3
4
6
5
1
1
TRUTH TABLE  
D0  
D1  
D0  
D1  
Q
Q
D
V
EE  
L
L
H
H
L
H
L
H
H
L
H
L
H
L
L
L
L
H
H
H
H
L
Figure 1. 8–Lead Pinout (Top View) and Logic Diagram  
H
L
ORDERING INFORMATION  
Device  
Package  
Shipping  
98 Units/Rail  
2500 Tape & Reel  
MC10EP05D  
SOIC  
MC10EP05DR2  
SOIC  
Semiconductor Components Industries, LLC, 1999  
1
Publication Order Number:  
September, 1999 – Rev. 1.0  
MC10EP05/D  

MC10EP05DR2 替代型号

型号 品牌 替代类型 描述 数据表
MC10EP05DR2G ONSEMI

完全替代

3.3V / 5V ECL 2−Input Differential AND/NAND
MC10EP05DG ONSEMI

完全替代

3.3V / 5VECL 2-Input Differential AND/NAND
MC10EP05D ONSEMI

完全替代

2-Input Differential AND/NAND

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10E SERIES, 2-INPUT XOR/XNOR GATE, PDSO8, SOIC-8