MC10ELT25, MC100ELT25
−5 VꢀDifferential ECL to TTL
Translator
Description
The MC10ELT/100ELT25 is a differential ECL to TTL translator.
Because ECL levels are used, a +5 V, −5.2 V (or −4.5 V) and ground
are required. The small outline 8-lead package and the single gate of
the ELT25 makes it ideal for those applications where space,
performance and low power are at a premium.
http://onsemi.com
MARKING DIAGRAMS*
The V pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
BB
8
8
8
HLT25
ALYW
G
KLT25
ALYW
G
1
differential input is connected to V as a switching reference voltage.
BB
V
may also rebias AC coupled inputs. When used, decouple V
BB
BB
SOIC−8
D SUFFIX
CASE 751
1
1
and V via a 0.01 mF capacitor and limit current sourcing or sinking
CC
to 0.5 mA. When not used, V should be left open.
BB
The 100 Series contains temperature compensation.
Features
8
8
1
8
• 2.6 ns Typical Propagation Delay
• 100 MHz F
• 24 mA TTL Outputs
• Flow Through Pinouts
1
HT25
KT25
ALYWG
ALYWG
CLK
MAX
TSSOP−8
DT SUFFIX
CASE 948R
G
G
1
• Operating Range: V = 4.5 V to 5.5 V with GND = 0 V;
CC
V
EE
= −4.2 V to −5.7 V with GND = 0 V
• Internal Input 50 KW Pulldown Resistors
• Q Output will default HIGH with inputs open or < 1.3 V
• Pb−Free Packages are Available
1
4
1
4
DFN8
MN SUFFIX
CASE 506AA
H
K
= MC10
= MC100
A
L
= Assembly Location
= Wafer Lot
5F = MC10
2U = MC100
Y
W
G
= Year
= Work Week
= Pb−Free Package
M
= Date Code
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
December, 2006 − Rev. 12
MC10ELT25/D