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MC10E431FNR2 PDF预览

MC10E431FNR2

更新时间: 2024-11-01 04:59:39
品牌 Logo 应用领域
安森美 - ONSEMI 触发器锁存器逻辑集成电路
页数 文件大小 规格书
4页 113K
描述
3-BIT DIFFERENTIAL FLIP-FLOP

MC10E431FNR2 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:QLCC包装说明:PLASTIC, LCC-28
针数:28Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:8.63
Is Samacsys:N其他特性:NECL MODE: VCC = 0V WITH VEE = -4.2V TO -5.7V
系列:10EJESD-30 代码:S-PQCC-J28
JESD-609代码:e0长度:11.505 mm
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:1000000000 Hz
湿度敏感等级:1位数:1
功能数量:3端子数量:28
最高工作温度:85 °C最低工作温度:
输出特性:OPEN-EMITTER输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC28,.5SQ封装形状:SQUARE
封装形式:CHIP CARRIER包装方法:TAPE AND REEL
峰值回流温度(摄氏度):240电源:-5.2 V
最大电源电流(ICC):132 mA传播延迟(tpd):0.85 ns
认证状态:Not Qualified座面最大高度:4.57 mm
子类别:FF/Latches最大供电电压 (Vsup):5.7 V
最小供电电压 (Vsup):4.2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:ECL
温度等级:OTHER端子面层:Tin/Lead (Sn/Pb)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
触发器类型:POSITIVE EDGE宽度:11.505 mm
最小 fmax:1100 MHzBase Number Matches:1

MC10E431FNR2 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC10E/100E431 is a 3-bit flip-flop with differential clock, data  
input and data output.  
The asynchronous Set and Reset controls are edge-triggered rather  
than level controlled. This allows the user to rapidly set or reset the  
flip-flop and then continue clocking at the next clock edge, without the  
necessity of de-asserting the set/reset signal (as would be the case with a  
level controlled set/reset).  
3-BIT DIFFERENTIAL  
FLIP-FLOP  
The E431 is also designed with larger internal swings, an approach  
intended to minimize the time spent crossing the threshold region and  
thus reduce the metastability susceptibility window.  
The differential input structures are clamped so that the inputs of  
unused registers can be left open without upsetting the bias network of  
the device. The clamping action will assert the D and the CLK sides of the  
inputs. Because of the edge triggered flip-flop nature of the device  
simultaneously opening both the clock and data inputs will result in an  
output which reaches an unidentified but valid state. Note that the input  
clamps only operate when both inputs fall to 2.5V below V  
.
CC  
Edge-Triggered Asynchronous Set and Reset  
FN SUFFIX  
PLASTIC PACKAGE  
CASE 776-02  
Differential D, CLK and Q; V  
BB  
Reference Available  
1100MHz Min. Toggle Frequency  
Extended 100E V Range of – 4.2V to – 5.46V  
EE  
Pinout: 28-Lead PLCC (Top View)  
V
CLK2 CLK2  
D
D
R
S
2
BB  
2
2
2
LOGIC DIAGRAM  
25  
24 23  
22  
21  
20  
19  
S
CLK1  
CLK1  
18  
17  
16  
15  
Q
Q
0
26  
2
D
D
S
0
D
Q
Q
Q
Q
27  
28  
1
0
2
0
R
1
V
CC  
CLK0  
CLK0  
0
V
R
S
EE  
Q
1
R
0
S
1
14  
13  
2
3
Q
1
0
S
1
D
1
Q
D
D
1
D
Q
Q
Q
Q
1
1
D
1
4
12  
Q
0
CLK1  
CLK1  
5
6
7
8
9
10  
11  
1
R
S
CLK0 CLK0  
D
D
R
S
V
CCO  
0
0
0
0
R
1
* All V  
CC  
and V  
CCO  
pins are tied together on the die.  
S
2
D
D
2
PIN NAMES  
Pin  
D
Q
Q
Q
Q
2
2
Function  
CLK2  
CLK2  
D[0:2], D[0:2]  
CLK[0:2], CLK[0:2]  
S[0:2]  
Differential Data Inputs  
Differential Clock  
Edge Triggered Set Inputs  
Edge Triggered Reset Input  
2
R
R
2
R[0:2]  
V
V
Reference Output  
BB  
Q[0:2], Q[0:2]  
BB  
Differential Data Outputs  
V
BB  
5/95  
Motorola, Inc. 1996  
REV 3  

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