MC10E451

更新时间： 2024-09-15 22:58:07

品牌	Logo	应用领域
安森美 - ONSEMI		时钟
页数	文件大小	规格书
4页	116K
描述
6-BIT D REGISTER DIFFERENTIAL DATA AND CLOCK

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数据手册

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MC10E451 数据手册

SEMICONDUCTOR TECHNICAL DATA

The MC10E/100E451 contains six D-type flip-flops with single-ended

outputs and differential data inputs. The common clock input is also

differential. The registers are triggered by a positive transition of the

positive clock (CLK) input.

A HIGH on the Master Reset (MR) input resets all Q outputs to LOW.

6-BIT D REGISTER

DIFFERENTIAL

DATA AND CLOCK

The V

output is intended for use as a reference voltage for

single-ended reception of ECL signals to that device only. When using for

this purpose, it is recommended that V

0.01µF capacitor.

is decoupled to V via a

The differential input structures are clamped so that the inputs of

unused registers can be left open without upsetting the bias network of

the device. The clamping action will assert the D and the CLK sides of the

inputs. Because of the edge triggered flip-flop nature of the device

simultaneously opening both the clock and data inputs will result in an

output which reaches an unidentified but valid state. Note that the input

clamps only operate when both inputs fall to 2.5V below V

• Differential Inputs: Data and Clock

• V

Output

FN SUFFIX

PLASTIC PACKAGE

CASE 776-02

• 1100MHz Min. Toggle Frequency

• Asynchronous Master Reset

• Extended 100E V

Range of – 4.2V to – 5.46V

• 75kΩ Input Pulldown Resistors

CCO

LOGIC DIAGRAM

CLK

Pinout: 28-Lead PLCC

(Top View)

CCO

* All V

and V

CCO

pins are tied together on the die.

PIN NAMES

Function

– D

+Data Input

– Data Input

CLK

+Clock Input

– Clock Input

Master Reset Input

– Q

Output

Data Outputs

12/93

Motorola, Inc. 1996

REV 2

2–1

12 3 4

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