MC10E445, MC100E445
5VꢀECL 4-Bit Serial/Parallel
Converter
Description
The MC10/100E445 is an integrated 4-bit serial to parallel data
converter. The device is designed to operate for NRZ data rates of up to
2.0 Gb/s. The chip generates a divide by 4 and a divide by 8 clock for
both 4-bit conversion and a two chip 8-bit conversion function. The
conversion sequence was chosen to convert the first serial bit to Q0, the
second to Q1 etc.
Two selectable serial inputs provide a loopback capability for testing
purposes when the device is used in conjunction with the E446 parallel to
serial converter.
http://onsemi.com
PLCC−28
FN SUFFIX
CASE 776
The start bit for conversion can be moved using the SYNC input. A
single pulse applied asynchronously for at least two input clock cycles
shifts the start bit for conversion from Qn to Qn−1. For each additional
shift required an additional pulse must be applied to the SYNC input.
Asserting the SYNC input will force the internal clock dividers to
“swallow” a clock pulse, effectively shifting a bit from the Qn to the Qn−1
output (see Timing Diagram B).
The MODE input is used to select the conversion mode of the device.
With the MODE input LOW, or open, the device will function as a 4-bit
converter. When the mode input is driven HIGH the data on the output will
change on every eighth clock cycle thus allowing for an 8-bit conversion
scheme using two E445’s. When cascaded in an 8-bit conversion scheme
the devices will not operate at the 2.0 Gb/s data rate of a single device.
Refer to the applications section of this data sheet for more information on
cascading the E445.
MARKING DIAGRAM*
1 28
MCxxxE445FNG
AWLYYWW
xxx
A
WL
YY
WW
G
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Upon power-up the internal flip-flops will attain a random state. To
synchronize multiple E445’s in a system the master reset must be asserted.
The V pin, an internally generated voltage supply, is available to this
BB
*For additional marking information, refer to
Application Note AND8002/D.
device only. For single-ended input conditions, the unused differential
input is connected to V as a switching reference voltage. V may also
BB
BB
rebias AC coupled inputs. When used, decouple V and V via a
BB
CC
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When
not used, V should be left open.
BB
The 100 Series contains temperature compensation.
Features
• On-Chip Clock ÷4 and ÷8
• ESD Protection: Human Body Model; > 2 kV,
Machine Model; > 100 V
• 2.0 Gb/s Data Rate Capability
• Differential Clock and Serial Inputs
• Meets or Exceeds JEDEC Spec EIA/JESD78
IC Latchup Test
• Moisture Sensitivity Level: Pb = 1; Pb−Free = 3
For Additional Information, see Application Note
AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 528 devices
• V Output for Single-Ended Input Applications
BB
• Asynchronous Data Synchronization
• Mode Select to Expand to 8-Bits
• PECL Mode Operating Range: V = 4.2 V to 5.7 V
CC
with V = 0 V
EE
• NECL Mode Operating Range: V = 0 V
CC
• PECL Mode Operating Range: V = 4.2 V to 5.7 V
CC
with V = −4.2 V to −5.7 V
EE
with V = 0 V
EE
• Internal Input 50 kW Pulldown Resistors
• Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
November, 2006 − Rev. 12
MC10E445/D
5秒后页面跳转
解析光耦仿真器：升级光耦合器技术的必要性
英伟达新一代Blackwell GPU过热问题致交付延迟
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
