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MC10E446 PDF预览

MC10E446

更新时间: 2024-09-14 22:58:07
品牌 Logo 应用领域
安森美 - ONSEMI 转换器
页数 文件大小 规格书
6页 129K
描述
4-BIT PARALLEL/ SERIAL CONVERTER

MC10E446 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC10E/100E446 is an integrated 4-bit parallel to serial data  
converter. The device is designed to operate for NRZ data rates of up to  
1.3Gb/s. The chip generates a divide by 4 and a divide by 8 clock for both  
4-bit conversion and a two chip 8-bit conversion function. The conversion  
sequence was chosen to convert the parallel data into a serial stream  
from bit D0 to D3. A serial input is provided to cascade two E446 devices  
for 8 bit conversion applications. Note that the serial output data clocks off  
of the negative input clock transition.  
4-BIT PARALLEL/  
SERIAL CONVERTER  
On Chip Clock ÷4 and ÷8  
1.5 Gb/s Typical Data Rate Capability  
Differential Clock and Serial Inputs  
V  
Output for Single-ended Input Applications  
BB  
Asynchronous Data Synchronization  
Mode Select to Expand to 8 Bits  
Internal 75kInput Pulldown Resistors  
Extended 100E V  
EE  
Range of -4.2V to -5.46V  
The SYNC input will asynchronously reset the internal clock circuitry.  
This pin allows the user to reset the internal clock conversion unit and  
thus select the start of the conversion process.  
FN SUFFIX  
PLASTIC PACKAGE  
CASE 776-02  
The MODE input is used to select the conversion mode of the device.  
With the MODE input LOW, or open, the device will function as a 4-bit  
converter. When the mode input is driven HIGH the internal load clock will  
change on every eighth clock cycle thus allowing for an 8-bit conversion scheme using two E446’s. When cascaded in an 8-bit  
conversion scheme the devices will not operate at the 1.3Gb/s data rate of a single device. Refer to the applications section of  
this data sheet for more information on cascading the E446.  
For lower data rate applications a V  
reference voltage is supplied for single-ended inputs. When operating at clock rates  
above 500MHz differential input signals are recommended. For single-ended inputs the V pin is tied to the inverting differential  
BB  
BB  
provides the switching reference for the input differential amplifier. The V  
input and bypassed via a 0.01µF capacitor. The V  
can also be used to AC couple an input signal, for more information on AC coupling refer to the interfacing section of the design  
guide in the ECLinPS data book.  
BB  
BB  
Pinout: 28-Lead PLCC (Top View)  
PIN NAMES  
D0  
D1  
D2  
D3 MODE NC  
NC  
Pin  
Function  
Differential Serial Data Input  
Parallel Data Inputs  
Differential Serial Data Output  
Differential Clock Inputs  
Differential ÷4 Clock Output  
Differential ÷8 Clock Output  
Conversion Mode 4-Bit/8-Bit  
Conversion Synchronizing Input  
25  
24  
23  
22  
21  
20  
19  
18  
SIN  
CLK  
CLK  
26  
27  
28  
1
NC  
NC  
D0 – D3  
SOUT, SOUT  
CLK, CLK  
CL/4, CL/4  
CL/8, CL/8  
MODE  
17  
16  
15  
14  
13  
12  
V
V
V
CC  
BB  
SOUT  
SOUT  
EE  
SYNC  
SIN  
SIN  
2
FUNCTION TABLES  
Mode  
3
V
CCO  
Conversion  
L
4-Bit  
8-Bit  
SYNC  
4
NC  
H
5
6
7
8
9
10  
11  
V
CL/8 CL/8 V  
CL/4 CL/4 V  
CCO  
CCO  
CCO  
7/96  
REV 2  
Motorola, Inc. 1996  

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